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maxim integrated products 1 some revisions of this device may incorporate deviations from published specifications known as errata. multiple revisions of any device may be simultaneously availabl e through various sales channels. for information about device errata, go to: www.maxim - ic.com/errata . for pricing, delivery, and ordering information, please contact maxim direct at 1 - 888 - 629 - 4642, or visit maxim?s website at www.maxim - ic.com. max 24287 1g bps parallel-to - serial mii converter general description the MAX24287 is a flexible, low - cost ethernet interface conversion ic. the parallel interface can be configured for gmii, rgmii, tbi, rtbi , or 10/100 mii , wh ile the serial interface can be configured for 1.25gbps sgmii or 1000base - x operation. in sgmii mode , the device interfaces directly to ethernet switch ics, asic macs , and 1000base - t electrical sfp modules. in 1000base - x mode , the device interfaces directl y to 1gbps 1000base - x sfp optical modules. the MAX24287 performs automatic translation of link speed and duplex autonegotiation between parallel mii mdio and the serial interface. microprocessor interaction is optional for device operation. hardware - config ured modes support sgmii master and 1000base - x autonegotiation without software involvement. this device is ideal for interfacing single - channel gmii/mii devices such as microprocessors, fpgas, network processors, ethernet - over - sonet or - pdh mapper s, and tdm - over - packet circuit emulation devices. the device also provides a convenient solution to interface such devices with electrical or optical ethernet sfp modules. applications any system with a need to interface a component with a parallel mii int erface (gmii, rgmii, tbi rtbi, 10/100 mii) to a component with an sgmii or 1000base - x interface switches and routers telecom equipment ordering information part temp range pin - package MAX24287 etk+ -40 c to +85c 68 tqfn -ep* + denotes a lead (pb) - free/rohs - compliant package. *ep = exposed pad. block diagram appears on page 7 . register map appears on page 41 . hig hlighted features ? bidirectiona l wire - speed ethernet interface conversion ? can interface directly to sfp modules and sgmii phy and switch ics ? serial interface configurable as 1000base - x or sgmii revision 1.8 (4 - , 6 - , or 8 - pin) ? parallel interface configurable as gmii, rgmii, tbi, rtbi , or 10/100 mii ? serial interface has clock and data recovery block (cdr) and does not require a clock input ? translates link speed and duplex mode negotiation between mdio and sgmii pcs ? supports 10/100 mii or rgmii operation with sgmii running at the same ra te ? configurable for 10/100 mii dte or dce modes (i.e. , c onnects to phy or mac) ? can also be configured as general - purpose 1:10 s er d es with optional comma alignment ? supports synchronous ethernet by providing a 25mhz or 125mhz recovered clock and accepti ng a transmit clock ? can provide a 125mhz clock for the mac to use as gtxclk ? accepts 10mhz, 12.8mhz, 25mhz or 125mhz reference clock ? can be pin - configured at reset for many common usage scenarios ? optional software control through mdio interface ? gpio pins c an be configured as clocks, status signals and interrupt outputs ? 1.2v operation with 3.3v i/o ? small , 8 mm x 8mm , 68- pin tqfn package 19 - 5987 ; rev 0; 7/11
_________________________________________________________________________________________________ MAX24287 2 table o f contents 1. application examples ............................................................................................................. 6 2. block diagram ........................................................................................................................... 7 3. detailed features ................................................................................................................... 7 4. acronyms, abbreviati ons, and glossary ...................................................................... 8 5. pin descriptions ........................................................................................................................ 8 6. functional descripti on ....................................................................................................... 16 6.1 p in c onfiguration d uring r eset ............................................................................................. 16 6.2 g eneral -p urpose i/o ................................................................................................................ 17 6.3 r eset and p rocessor i nterrupt ............................................................................................. 18 6.4 mdio i nterface ......................................................................................................................... 19 6.5 s erial i nterface ? 1000base - x or sgmii ............................................................................... 23 6.6 p arallel i nterface ? gmii, rgmii, tbi, rtbi, mii .................................................................... 24 6.7 a uto -n egotiation (an) .............................................................................................................. 30 6.8 d ata p aths ................................................................................................................................. 35 6.9 t iming p aths ............................................................................................................................... 36 6.10 l oopbacks ............................................................................................................................... 38 6.11 d iagnostic and t est f unctions ............................................................................................ 39 6.12 d ata p ath l atencies .............................................................................................................. 39 6.13 b oard d esign r ecommendations .......................................................................................... 39 7. register description s ......................................................................................................... 41 7.1 r egister m ap ............................................................................................................................. 41 7.2 r egister d escription s .............................................................................................................. 41
_________________________________________________________________________________________________ MAX24287 3 7.2.1 bmcr ................................ ................................ ................................ ................................ ................... 42 7.2.2 bmsr ................................ ................................ ................................ ................................ ................... 43 7.2.3 id1 and id2 ................................ ................................ ................................ ................................ .......... 44 7.2.4 an_adv ................................ ................................ ................................ ................................ ............... 45 7.2.5 an_rx ................................ ................................ ................................ ................................ ................. 45 7.2.6 an_exp ................................ ................................ ................................ ................................ ............... 45 7.2.7 ext_stat ................................ ................................ ................................ ................................ ........... 46 7.2.8 jit_diag ................................ ................................ ................................ ................................ ............. 46 7.2.9 pcscr ................................ ................................ ................................ ................................ ................. 47 7.2.10 gmiicr ................................ ................................ ................................ ................................ ................ 48 7.2.11 cr ................................ ................................ ................................ ................................ ........................ 49 7.2.12 ir ................................ ................................ ................................ ................................ .......................... 50 7.2.13 pagesel ................................ ................................ ................................ ................................ ............ 51 7.2.14 id ................................ ................................ ................................ ................................ .......................... 52 7.2.15 gpiocr1 ................................ ................................ ................................ ................................ ............. 52 7.2.16 gpiocr2 ................................ ................................ ................................ ................................ ............. 52 7.2.17 gpiosr ................................ ................................ ................................ ................................ ............... 53 8. jtag and boundary sc an .................................................................................................... 54 9. electrical character istics .............................................................................................. 58 9.2.1 cmos/ttl dc characteristics ................................ ................................ ................................ ............ 59 9.2.2 sgmii/1000base - x dc characteristics ................................ ................................ .............................. 59 9.3.1 refclk ac characteristics ................................ ................................ ................................ ................ 60 9.3.2 sgmii/1000base - x interface receive ac characteristics ................................ ................................ . 60 9.3.3 sgmii/ 1000base - x interface transmit ac characteristics ................................ ................................ 60 9.3.4 parallel interface receive ac characteristics ................................ ................................ ..................... 61 9.3.5 parallel inte rface transmit ac characteristics ................................ ................................ .................... 63 9.3.6 mdio interface ac characteristics ................................ ................................ ................................ ...... 65 9.3.7 jtag interface ac characteristics ................................ ................................ ................................ ...... 66 10. pin assignments ...................................................................................................................... 67 11. package and thermal information ................................................................................ 68 12. data sheet revision history .............................................................................................. 69
_________________________________________________________________________________________________ MAX24287 4 list of figures figure 2 - 1. block diagram ................................ ................................ ................................ ................................ ........... 7 figure 6 - 1. mdio slave state machine ................................ ................................ ................................ ..................... 20 figure 6 - 2. management information flow options, case 1,tri - mode phy ................................ ............................. 21 figure 6 - 3. management inf ormation flow options, case 2, sgmii switch chip ................................ .................... 21 figure 6 - 4. management information flow options, case 3, 1000base - x interface ................................ .............. 22 figure 6 - 5. recommended external components for high - speed serial interface ................................ ................. 23 figure 6 - 6. auto - negotiation with a link partner over 1000base - x ................................ ................................ ........ 31 figure 6 - 7. 1000base - x auto - negotiation tx_config_reg and rx_config_reg fields ................................ ........... 31 figure 6 - 8. sgmii control information generation, reception and acknowledgement ................................ ............ 33 figure 6 - 9. sgmii tx_config_reg and rx_config_reg fields ................................ ................................ .................. 33 figure 6 - 10. timing path diagram ................................ ................................ ................................ ............................. 36 figure 6 - 11. recommended refclk oscillator wiring ................................ ................................ ........................... 40 figure 8 - 1. jtag block diagram ................................ ................................ ................................ ............................... 54 fi gure 8 - 2. jtag tap controller state machine ................................ ................................ ................................ ...... 56 figure 9 - 1. mii/gmii/rgmii/tbi/rtbi receive timing waveforms ................................ ................................ .......... 61 figure 9 - 2. mii /gmii/rgmii/tbi/rtbi transmit timing waveforms ................................ ................................ ......... 63 figure 9 - 3. mdio interface timing ................................ ................................ ................................ ............................ 65 figure 9 - 4. jtag timing diagram ................................ ................................ ................................ ............................. 66
_________________________________________________________________________________________________ MAX24287 5 list o f tables table 5 - 1. pin type definitions ................................ ................................ ................................ ................................ .... 8 table 5 - 2. detailed pin descriptions ? globa l pins (3 pins) ................................ ................................ ....................... 8 table 5 - 3. detailed pin descriptions ? mdio interface (2 pins) ................................ ................................ ................. 9 table 5 - 4. detailed pin descriptions ? jtag interface (5 pins) ................................ ................................ .................. 9 table 5 - 5. detailed pin descriptions ? gpio signals (5 dedicated pins, 4 shared pins) ................................ ............ 9 table 5 - 6. detai led pin descriptions ? sgmii/1000base - x serial interface (7 pins) ................................ .............. 10 table 5 - 7. detailed pin descriptions ? parallel interface (25 pins) ................................ ................................ ........... 11 table 5 - 8. detailed pin descriptions ? power and ground pins (15 pins) ................................ ................................ 15 table 6 - 1. reset configuration pins, 15 - pin mode (col=0) ................................ ................................ .................... 16 table 6 - 2. parallel interface configuration ................................ ................................ ................................ ................ 16 table 6 - 3. reset configuration pins, 3 - pin mode (col=1) ................................ ................................ ...................... 17 table 6 - 4. gpo1, gpio1 and gpio3 configuration options ................................ ................................ ................... 17 table 6 - 5. gpo2 and gpio2 configuration options ................................ ................................ ................................ . 17 table 6 - 6. gpio 4, gpio5, gpio6 and gpio7 configuration options ................................ ................................ ..... 18 table 6 - 7. parallel interface modes ................................ ................................ ................................ ........................... 24 table 6 - 8. gmii parallel bus pin nam ing ................................ ................................ ................................ .................. 24 table 6 - 9. tbi parallel bus pin naming (normal mode} ................................ ................................ ........................... 25 table 6 - 10. tbi parallel bus pin naming (one - clock mode) ................................ ................................ ................... 25 table 6 - 11. rgmii parallel bus pin naming ................................ ................................ ................................ ............. 27 table 6 - 12. rtbi parallel bus pin naming ................................ ................................ ................................ ............... 28 table 6 - 13. mii parallel bus pin naming ................................ ................................ ................................ ................... 29 table 6 - 14. an_adv 1000base - x auto - negotiation ability advertisement register (mdio 4) .............................. 31 table 6 - 15. an_rx 1000base - x auto - negotiation ability receive register (mdio 5) ................................ ........... 32 table 6 - 16. an_adv sgmii configuration information register (mdio 4) ................................ .............................. 34 table 6 - 17. an_rx sgmii configuration information receive register (mdio 5) ................................ .................. 34 table 6 - 18. timing path muxes ? no loopback ................................ ................................ ................................ ....... 36 table 6 - 19. timing path muxes ? dlb loopback ................................ ................................ ................................ ..... 36 table 6 - 20. timing path muxes ? rlb loopback ................................ ................................ ................................ ..... 37 table 6 - 21. gmii data path latencies ................................ ................................ ................................ ...................... 39 table 7 - 1. register map ................................ ................................ ................................ ................................ ............ 41 table 8 - 1. jtag instruction codes ................................ ................................ ................................ ........................... 56 table 8 - 2. jtag id code ................................ ................................ ................................ ................................ .......... 57 table 9 - 1. recommended dc operating conditions ................................ ................................ ................................ 58 table 9 - 2. dc characteristics ................................ ................................ ................................ ................................ .... 58 table 9 - 3. dc characteristics for parallel and mdio interfaces ................................ ................................ ............... 59 ta ble 9 - 4. sgmii/1000base - x transmit dc characteristics ................................ ................................ ................... 59 table 9 - 5. sgmii/1000base - x receive dc characteristics ................................ ................................ .................... 59 table 9 - 6. refclk ac characteristics ................................ ................................ ................................ .................... 60 table 9 - 7. 1000base - x and sgmii receive ac characteristics ................................ ................................ ............. 60 table 9 - 8. 1000base - x and sgmii rec eive jitter tolerance ................................ ................................ .................. 60 table 9 - 9. sgmii and 1000base - x transmit ac characteristics ................................ ................................ ............ 60 table 9 - 10. 1000base - x transmit jitter characteristics ................................ ................................ .......................... 60 table 9 - 11. gmii and tbi receive ac characteristics ................................ ................................ ............................. 61 table 9 - 12. rgmii - 1000 and rtbi receive ac characte ristics ................................ ................................ ............... 62 table 9 - 13. rgmii - 10/100 receive ac characteristics ................................ ................................ ............................ 62 table 9 - 14. mii ? dce receive ac characteristics ................................ ................................ ................................ .... 62 table 9 - 15. mii ? dte receive ac characteristics ................................ ................................ ................................ .... 63 table 9 - 16. gmii, tbi, rgmii - 1000 and rtbi transmit ac characteristics ................................ ............................ 63 table 9 - 17. rgmii - 10/100 transmit ac characteristics ................................ ................................ ........................... 64 table 9 - 18. mii ? dce transmit ac characteristics ................................ ................................ ................................ ... 64 table 9 - 19. mii ? dte transmit ac characteristics ................................ ................................ ................................ ... 64 table 9 - 20. mdio interface ac characteristics ................................ ................................ ................................ ........ 65 table 9 - 21. jtag interface timing ................................ ................................ ................................ ............................ 66 table 11 - 1. package thermal properties, natural convection ................................ ................................ ................. 68
_________________________________________________________________________________________________ MAX24287 6 1. application examples sgmii phy rd td tclk 625 mhz m a c rxd[7:0] txd[7:0] rx_clk 125 mhz tx_clk 125 mhz max 24287 processor, asic, fpga a) copper media cdr optical module d) fiber module 1000base-sx/lx c1) long pcb trace card-to-card max 24287 cdr 100 ohm pcb trace 100 ohm pcb trace c o n n e c t o r c o n n e c t o r gmii phy c2) ethernet switch chip b) connect parallel mii component to sgmii component rd td tclk 625 mhz m a c rxd[7:0] txd[7:0] rx_clk 125 mhz tx_clk 125 mhz max 24287 processor, asic, fpga cdr m a c m a c rxd[7:0] txd[7:0] rx_clk 125 mhz tx_clk 125 mhz max 24287 processor, asic, fpga cdr rd td td rd txd[7:0] rxd[7:0] txclk 125 mhz rxclk 125 mhz 100 ohm pcb trace 100 ohm pcb trace c o n n e c t o r c o n n e c t o r sgmii phy m a c txd[7:0] rx_clk 125 mhz tx_clk 125 mhz max 24287 processor, asic, fpga cdr rd td td rd m a c txd[7:0] rx_clk 125 mhz tx_clk 125 mhz max 24287 processor, asic, fpga cdr rd td rxd[7:0] rxd[7:0] (optional) (optional)
_________________________________________________________________________________________________ MAX24287 7 2. block diagram figure 2 - 1 . block diagram receive gmii rgmii tbi rtbi mii rxd[7:0] rxclk rx_dv rx_er col crs d c d c pcs decoder (10b/8b) rd[9:0] 125mhz receive cdr rdp rdn transmit gmii rgmii tbi rtbi mii txd[7:0] txclk gtxclk tx_en tx_er d c d c pcs encoder (8b/10b) td[9:0] 125mhz de- serializer rd 1.25ghz serializer transmit driver td 625mhz tdp tdn tclkp tclkn control and status gpio control tx pll refclk mdio mdc rst_n gpio1 gpio2 gpio3 gpo1 gpo2 MAX24287 auto- negotiate gpio4 gpio5 gpio6 gpio7 tlb loopback dlb loopback rate adaption buffer rate adaption buffer alos rlb loopback 125mhz 125mhz, 62.5mhz, 25mhz, 2.5mhz 625mhz 3. detailed features general features ? high - speed mdio interface (12.5mhz slave only) with optional preamble suppression ? can be pin - configured at reset for many common usage scenarios ? operates fro m a 10, 12.8, 20, 25 , or 125mhz reference clock ? optional 125mhz output clock for mac to use as gtxclk parallel - serial mii conversion features ? bidirectional wire - speed interface conversion ? serial interface: 1000base - x or sgmii revision 1.8 (4 - , 6 - , or 8 - pin ) ? parallel interface: gmi i, rgmii (10, 100 and 1000mbps) , tbi, rtbi or 10/100 mi i (dte or dce) ? 8 - pin source - clocked sgmii m ode ? 4 - pin 1000base - x serdes mode to interface with optical m odules ? connects processors with parallel mii interfaces to 1000ba se- x sfp optical modules ? connects processors with parallel mii interfaces to phy or switch ics with sgmii interfaces ? interface conversion is transparent to mac layer and higher layers ? translates link speed and duplex mode between gmii/mii mdio and sgmii p cs ? configurable for 10/100 mii dte or dce modes (i.e. , connects to phy or mac) synchronous ethernet features ? receive path bit clock can be output on a gpio pin to line - time the system from the ethernet port ? transmit path can be frequency - locked to a system clock signal connected to the refclk pin
_________________________________________________________________________________________________ MAX24287 8 4. acronyms, abbreviations, and glossary ? d ce data communication equipment ? ddr dual data rate (data driven and latched on both clock edges) ? dte data terminating equipment ? pcb printed circuit board ? phy physical. refer s to either a transceiver device or a protocol layer ? ingress the serial (sgmii) to parallel (gmii) direction ? egress the parallel (gmii) to serial (sgmii) direction ? receive the serial (sgmii) to parallel (gmii) direction ? transmit the parallel (gmii) to serial (sgmii) direction 5. pin descriptions n ote that some pins have different pin names and functions under different configuration s. table 5 - 1 . pin type definition s type definition i input idiff input , differential ipu i nput, with pullup ip d i nput, with p ulldown io bi directional io r bi directional , sampled at reset ioz bi dire ctional, can go high impedance o output o diff output , differential (cml) oz output, can go high impedance table 5 - 2 . detailed pin descriptions ? global pins ( 2 p ins) pin name pin # type pin description rst_n 67 i reset (active low, asynchronous) this signal resets all logic, state machines and registers in the device. pin s tates are sampled and used to set the default values of several register fields as described in 6.1 . rst_n should be held low for at least 100 s. see section 6.3.1 . refclk 68 i reference clock this signal is the reference clock for the device. the frequency can be 10mhz, 12.8mhz , 25mhz or 125mhz 100 ppm. at reset the frequency is specified using the rxd[3:2] pins (see section 6.1 ). the refclk signal is the input clock to the tx pll. see section 6.9 .
_________________________________________________________________________________________________ MAX24287 9 table 5 - 3 . detailed pin descriptions ? mdio interface (2 pins) pin name pin # type pin description mdc 41 i mdio clock . mdc is the clock signal of the 2 - wire mdio interface. it can be any frequency up to 12.5mhz. see section 6.4 . mdio 42 ioz mdi o data . this is the bidirectional, half - duplex data signal of the mdio interface . it is sampled and updated on positive edges of mdc. ieee 802.3 requires a 2k ? 5% pulldown resistor on this signal at the mac. see section 6.4 . table 5 - 4 . detailed pin descriptions ? jtag interface (5 pins) pin name pin # type pin description jtrst_n 43 i jtag test reset (active low). asynchronously resets the test access port (tap) c ontroller. if not used, connect to d vdd33 or dvss . see section 8 . jtclk 21 i jtag test clock. this clock signal can be any frequency up to 10mhz. jtdi and j tms are sampled on the rising edge of jtclk, and jtdo is updated on the falling edge of jtclk. if not used, connect to dvdd33 or dvss . see section 8 . jtms 22 i jtag test mode select. sampled on the rising edge of jtclk . u sed to place the port into the various def ined ieee 1149.1 states. if not used , co nnect to d vdd33 . see section 8 . jtdi 23 i jtag test data input. test instructions and data are clocked in on this pin on the rising edge of jtclk. if not used, connect t o d vdd33. see section 8 . jtdo 44 oz jtag test data output. test instructions and data are clocked out on this pin on the falling edge of jtclk. if not used leave unconnected . see section 8 . table 5 - 5 . detailed pin descriptions ? gpio signals (5 dedicated pins , 4 shared pins ) pin name pin # type pin description gpo1 24 ior general purpose output 1. after reset, this pi n can either be high impedance (tbi or rtbi mode) or an output that indicates link status, 0=link down, 1=link up. the function can be changed after reset. see section 6.2 . gpo2 25 ior general purpose o utput 2. after reset, this pin can either be high impedance (tbi or rtbi mode) or an output that indicates crs (carrier sense) . the function can be changed after reset. see section 6.2 . gpio1 61 ioz general purp ose input or output 1. after reset this pin can be either high impedance or generating a 125mhz clock signal. gpo1=0 at reset: after reset, gpio1 is high impedance. gpo1=1 at reset: after reset, gpio1 is 125mhz clock out the function can be changed after r eset. see section 6.2 . gpio2 60 ioz general purpose input or output 2. after reset this pin is high impedance. the function can be changed after reset. see section 6.2 . gpio3 59 ioz general purpose input or output 3. after reset this pin is high impedance. the function can be changed after reset. see section 6.2 .
_________________________________________________________________________________________________ MAX24287 10 pin name pin # type pin description gpio4/txd[4] 52 ioz general purpose input or outpu t 4. available for use as a gpio pin when the parallel interface is configured for mii , rgmii or rtbi modes . after reset this pin is high impedance. the function can be changed after reset. see section 6.2 . gpio5/txd[5] 53 ioz general purpose input or o utput 5. available for use as a gpio pin when the parallel interface is configured for mii , rgmii or rtbi modes . after reset this pin is high impedance. the function can be changed after reset. see section 6.2 . gpio6/txd[6] 54 ioz general purpose input or o utput 6. available for use as a gpio pin when the parallel interface is configured for mii , rgmii or rtbi modes . after reset this pin is high impedance. the f unction can be changed after reset. see section 6.2 . gpio7/txd[7] 55 ioz g eneral purpose input or o utput 7. available for use as a gpio pin when the parallel interface is configured for mii , rgmii or rtbi mo des . after reset this pin is high impedance. the function can be changed after reset. see section 6.2 . table 5 - 6 . detailed pin descriptions ? sgmii /1000base - x serial interface (7 pins) pin name pin # type pin description tdp , tdn 9 8 o diff transmit data output these pins form a differential cml output for the 1.25gbaud sgmii transmit signal to a neighboring 1000base - x optical module (sfp, etc.) or phy with sgmii interface. see section 6.5 . tclkp , tclkn 6 5 o diff transmit clock output these pins form a differential cml output for an optional 625mhz clock for the sgmii transmit signal on tdp/tdn. this output is di sabled at reset but is enabled by setting cr .tclk_en=1. see section 6.5 . rdp , rdn 13 14 idiff receive data input these pins form a differential input for the 1.25gbau d sgmii receive signal from a neighboring 1000base - x optical module (sfp, etc.) or phy with sgmii interface. a receive clock signal is not necessary because the device uses a built - in cdr to recover the receive clock from the signal on rdp/rdn. see section 6.5 . alos 19 i analog loss of signal this pin receives analog loss - of - signal from a neighboring optical transceiver module. if the o ptical module does not have an alos output , this pin should be connected to d vss for proper operation. see section 6.5 . 0 = alos not detected or not required , normal operation 1 = alos detected , loss of signal
_________________________________________________________________________________________________ MAX24287 11 table 5 - 7 . detailed pin de scriptions ? parallel interface (25 pins) pin name pin # type pin description rxclk 40 i o receive clock in all modes the frequency tolerance is 100 ppm. gmii mode : rxclk is the 125mhz receive clock . rgmii mode s : rxclk is the 125mhz (rgmii - 1000), 25mhz (rgmii - 100) or 2.5mhz (rgmii - 10) receive clock (ddr). tbi mode : in normal tbi mode ( gmiicr .tbi_rate=1 or rx_dv=1 at reset), rxclk is the 62.5mhz receive clock for odd code groups and txclk/rcxclk1 is the 62.5mhz receive clock for even code groups. in one - clock tbi mode ( gmiicr .tbi_rate=0 or rx_dv=0 at reset), rxclk is the 125mhz receive clock. rtbi mode : rxclk is the 125mhz receive clock (ddr). mii mode : rxclk is the 25mhz (100mbps mii) or 2.5mhz (10mbps mii) receive clock. in dte mode (dce_ dte )=1 , rxclk is an input. in dce mode (dce_ dte )=0, rxclk is an output. rxd[0] rxd[1] rxd[2] rxd[3] rxd[4] rxd[5] rxd[6] rxd[7] 38 37 36 35 34 33 32 31 i o r i or i or i or i or i or i or i or receive dat a outputs during reset these pins are configuration inputs. see section 6.1 . after reset they are driven as outputs. gmii mode : receive_data[7:0] is output on rxd[7:0] on the rising edge of rxclk. mii , rgmii - 10 and rgmii - 100 modes : receive_data[3:0] is output on rxd[3:0] on the rising edge of rxclk. rx d[7:4] are high impedance. rgmii - 1000 mode : receive_data[3:0] is output on rxd[3:0] on the rising edge of rxclk, and receive_data[7:4] is output on the falling edge of rxclk. rx d[7:4] are high impedance. tbi mode : in normal tbi mode ( gmiicr .tbi_rate=1 or rx_dv=1 at reset), receive_data[7:0] is output on rxd[7:0], receive_data[8] is output on rx_dv, and receive_data[9] is output on rx_er on the rising edge of rxclk and the rising edge of rxclk1 (both 62.5mhz, 180 degrees out of phase). in one - clock tbi mode ( gmiicr .tbi_rate=0 or rx_dv=0 at reset), these same signals are output on the rising edge of rxclk (125mhz). rtbi mode : receive_data[3:0] is output on rxd[3:0] and receive_data[4 ] is output on rx_dv on the rising edge of rxclk. receive_data[8:5] is output on rxd[3:0] and receive_data[9] is out put on rx_dv on the falling edge of rxclk. rx d[7:4] are high impedance.
_________________________________________________________________________________________________ MAX24287 12 pin name pin # type pin description rx_dv 29 i o r receive data valid during reset this pin is a configuration input. see section 6.1 . after reset it is driven as an output. mii mode and gmii mode : rx_dv is output on the rising edge of rx clk . rgmii mode s : the rx_ctl signal is output on rx_dv on both edges of rxclk. tbi mode : in normal tbi mode ( gmiicr .tbi_rate=1 or rx_dv=1 at reset), receive_data[8] is output on rx_dv on the rising edge of rxclk and the rising edge of rxclk1 ( both 62.5mhz, 180 degrees out of phase). in one - clock tbi mode ( gmiicr .tbi_rate=0 or rx_dv=0 at reset), receive_data[8] is output on rx_dv on the rising edge of rxclk (125mhz). rtbi mode : receive_data[4} is output on rx_dv on the rising edge of rxclk. receive_data[9] is output on rx_dv on the falling edge of rxclk. rx_er 28 i o r receive error during reset this pin is a configuration input. see section 6.1 . after reset it is driven as an output. mii mode and gmii mode : rx_er is output on the rising edge of rx clk . rgmii mode and rtbi mode : rx_er pin is high impedance. tbi mode : in normal tbi mode ( gmiicr .tbi_rate=1 o r rx_dv=1 at reset), receive_data[9] is output on rx_er on the rising edge of rxclk and the rising edge of rxclk1 (both 62.5mhz, 180 degrees out of phase). in one - clock tbi mode ( gmiicr .tbi_rate=0 or rx_dv=0 at reset), receive_data[9] is output on the rising edge of rxclk (125mhz). col 27 i o r collision detect during reset this pin is a configuration input. see section 6.1 . after reset it is driven as an output. mi i mode . gmii mode and rgmii mode s : col indicate s that a tx/rx collision is occurring. it is meaningful only in half duplex operation. it is asynchronous to any of the clocks. col is driven low at all times when bmcr .dlb=1 and bmcr .col_test=0. when bmcr .dlb=1 and bmcr .col_test=1, col behaves as described in the col_test bit description. 1 = collision is occurring 0 = col lision is not occurring tbi mode and rtbi mode : this pin is high impedance.
_________________________________________________________________________________________________ MAX24287 13 pin name pin # type pin description crs /comma 26 i o r carrier sense / comma detect during reset this pin is a configuration input. see section 6.1 . after reset it is driven as a n output. mii mode . gmii mode and rgmii mode s : crs is asserted by the device when either the transmit data path or the receive data path is active. this signal is asy nchronous to any of the clocks. tbi mode and rtbi mode : comma is asserted by the device when a comma pattern is detected in the receive data stream. in normal tbi mode ( gmiicr .tbi_rate=1 or rx_dv=1 at reset), comma is updated on the rising edge of rxclk and the rising edge of rxclk1 (both 62.5mhz, 180 degrees out of phase). in one - clock tbi mode ( gmiicr .tbi_rate=0 or rx_dv=0 at reset) and rtbi mode, comma is updated on the rising edge of rxclk (125mhz). txclk / rxclk1 46 io mii transmit clock when txclk is an input, frequency tolerance is 100ppm. m ii mode : txclk is the 25 mhz (100mbps mii) or 2.5mhz 10mbps mii) transmit clock. in dte mode (dce_ dte )=1 , txclk is an input. in dce mode (dce_ dte )=0, txclk is an output. gmii mode , rgmii mode and rtbi mode : txclk can output a 125mhz clock for use by neighboring components (e.g. a mac) when gmiicr .txc lk_en=1 (or txclk=1 at reset). tbi mode : in normal tbi mode ( gmiicr .tbi_rate=1 or rx_dv=1 at reset), this pin becomes the 62.5mhz rxclk1 output for even code group s. in one - clock tbi mode ( gmiicr .tbi_rate=0 or rx_dv=0 at reset), txclk can output a 125mhz clock for use by neighboring components (e.g. a mac) when gmiicr .tx clk_en=1 (or txclk=1 at reset). gtxclk 66 i gmii/rgmii transmit clock in all modes the frequency tolerance is 100ppm. gmii mode : gtxclk is the 125mhz transmit clock . rgmii mode s : gtxclk is the 125mhz (rgmii - 1000), 25mhz (rgmii - 100) or 2.5mhz (rgmii - 10) transmit clock (ddr). tbi mode : gtxclk is the 125mhz transmit clock. rtbi mode : gtxclk is the 125mhz transmit clock (ddr). mii mode : this pin is not used and should be pulled low. see the txclk pin description.
_________________________________________________________________________________________________ MAX24287 14 pin name pin # type pin description txd[0] txd[1] txd[2] txd[3] txd[4]/gpio4 txd[5]/gpio5 txd[6]/gpio6 txd[7]/gpio7 48 49 50 51 52 53 54 55 i i i i ioz ioz ioz ioz transmit data inputs depending on the parallel mii interface mode, four or eight of these pins are used to accept transmit data from a neighboring component. gmii mode : the rising edge of gtxclk latches transmit_data[7:0] from tx d [7:0]. mii , rgmii - 10 and rgmii - 100 modes : the rising edge of txclk (mii) or gtxclk (rgmii) latche s transmit_data[3:0] from txd[3:0]. txd[7:4] become gpio7 ? gpio4. rgmii - 1000 mode : the rising edge of gtxclk latches transmit_data[3:0] from txd[3:0]. the falling edge of gtxclk latches transmit_ data[7:4] from txd[3:0]. txd[7:4] become gpio7 ? gpio4. tbi mode : the rising edge of gtxclk latches transmit_data[7:0] from txd[7:0], transmit_data[8] from tx_en and transmit_data[9] from tx_er. rtbi mode : the risi ng edge of gtxclk latches transmit_data[3:0] from txd[3:0] and transmit_data[4] from tx_en. the falling edge of gtxclk latches transmit_data[8:5] from txd[3:0] and transmit data[9] from tx_en. txd[7:4] become gpio7 ? gpio4. tx_en 57 i transmit enable mii mode and gmii mode : the rising edge of txclk (mii) or gtxclk (gmii) latches the tx_en signal from this pin. rgmii mode s : both edges of gtxclk latch t he tx_ctl signal from this pin. tbi mode : t he rising edge of gtxclk latches transmit_data[7:0] from txd[7:0], transmit_data[8] from tx_en an d transmit_data[9] from tx_er. rtbi mode : the risi ng edge of gtxclk latches transmit_data[3:0] from txd[3:0] and transmit_data[4] from tx_en. the falling edge of gtxclk latches transmit_data[8:5] from tx d[3:0] and transmit data[9] from tx_en. tx_er 58 i transmit error mii mode and gmii mode : the rising edge of txclk (mii) or gtxclk (gmii) latches the tx_er signal from this pin. rgmii mode s : this pin is not used. tbi mode : the rising edge of gtxclk latches transmit_data[7:0] from txd[7:0], transmit_data[8] from tx_en and transmit_data[9] from tx_er . rtbi mode : this pin is not used.
_________________________________________________________________________________________________ MAX24287 15 table 5 - 8 . detailed pin descriptions ? power and ground pins ( 1 7 pins) pin name pin # pin description dvdd12 30, 56 di gital power supply, 1.2v (2 pins) dvdd33 20, 39 , 65 digital power supply, 3.3v dvss 47 return for dvdd12 and dvdd33 rvdd12 16 1.25g receiver analog power supply, 1.2v rvdd33 12 1.25g receiver analog power supply, 3.3v rvss 15 return for rvdd12 and rv dd33 tvdd12 11 1.25g transmitter analog power supply, 1.2v tvdd33 7 1.25g transmitter analog power supply, 3.3v tvss 10 return for tvdd12 and tvdd33 cvdd12 3 tx pll analog power supply, 1.2v cvdd33 2 tx pll analog power supply, 3.3v cvss 4 return for cvdd12 and cvdd33 gvdd12 18 analog power supply, 1.2v gvss 1 return for gvdd12. exposed pad ep exposed pad ( die paddle). connect to ground plane. ep also functions as a heatsink. solder to the circuit - board ground plane to maximize thermal dissipation.
_________________________________________________________________________________________________ MAX24287 16 6. functional d escription 6.1 pin configuration during reset the max 24287 initial configuration is determined by pins that are sampled at reset . the values on these pins are used to set the reset values of several register bits . the pins that are sampled at reset to pin - configure the device are listed described in table 6 - 1 . d uring reset these pins are high - impedance inputs and require 10 k ? pullup or pull down resistor s to s et pin - configuration value s . after reset , the pins can become outputs if configured to do so and operate as configured. there are two pin configuration modes: 15 - pin mode and 3 - pin mode. in 15 - pin mode (col =0 during reset , see table 6 - 1 ) all major settings associated with the pcs block are configurable. in addition, the input reference clock frequency on the refclk pin is configured during reset using the rxd[3:2] pins . table 6 - 1 . reset configuration pins, 15 - pin mode (col=0) pin function register bit affected notes crs double date rate gmiicr : ddr=crs see table 6 - 2 . gpo2 10/100 mii: dte or dce 10/100 mii: gmiicr : dte_dce 0=dce, 1=dt e (serial interface is configured for sgmii mode, pcscr :basex=0) other: serial interface other: pcscr :basex 0=sgmii, 1=1000base=x gpo1 gpio1 configuration gpiocr1 .gpio1_sel[2] 0=high impedance 1=125mhz from tx pll rxd[1:0] parallel interface speed gmiicr : spd[1:0] see table 6 - 2 . rxd[3:2] refclk frequency none 00=10mhz, 01=12.8mhz, 10=25mhz, 11=125mhz rxd[7:4] mdio phyad [3:0]. internal mdio phyad register (device address on mdio bus). note: phyad[4:0]=11111 enables factory test mode. do not use. rx_er mdio phyad [4]. rx_dv tbi mode gmiicr :t bi_rate 0=one - clock mode (125mhz) 1=normal mode (62.5mhz x 2) other: auto - negoti ation bmcr : an_ en 0=disable, 1=enable txclk txclk enable gmiicr :txclk_en 0=high impedance 1=125mhz from tx pll ignored in mii mode and tbi with two 62.5mhz rx clo cks table 6 - 2 . parallel interface configuration spd[1] spd[0] speed ddr=0 ddr=1 0 0 10mbps mii rgmii - 10 0 1 100mbps mii rgmii - 100 1 0 1000mbps gmii rgmii - 1000 1 1 1000mbps tbi rtbi in 3 - pin mode (col=1 during reset , see table 6 - 3 ) the device is configured for a 1000mbps rgmii or gmii parallel interface. this mode is targeted to the application of c onnecting an asic, fpga or processor with a n rgmii or gm ii interface to a switch device with a n sgmii interface or to a 1000base - x optical interface . in 3 - pin mode, the refclk pin is configured for 25 mhz, the phy address is set to 0x04 , 1000base - x auto - negotiation (or automatic transmission of sgmii control in f ormation) is enabled, txclk is configured to output a 125mhz clock, and the tclkp/tclkn differential pair is disabled .
_________________________________________________________________________________________________ MAX24287 17 table 6 - 3 . reset configuration pins, 3 - pin mode (col=1) pin function register bit affecte d notes crs double date rate gmiicr : ddr=crs 0=gmii, 1=rgmii gpo2 serial interface pcscr :basex 0=sgmii, 1=1000base=x note: in 3 - pin mode register fields are au tomatically set as follows: refclk clock rate to 25mhz , gmiicr :spd[1:0]=10, mdio phyad is set to 0x04, bmcr :an_en=1, gmii cr :txclk_en=1, gpiocr1 =0 and gpiocr2 =0. all other registers are reset to normal defaults listed in the register descriptions. 6.2 g eneral - purpose i/ o the m ax 24287 has two general - purpose output pins, gpo1, gpo2, and seven general - purpose input/output pins, gpio1 through gpio7. each pin can be configured to drive low or high or be in a high - impedance state. other uses for the gpo and gpio pins are listed in table 6 - 4 through table 6 - 6 . the gpo and gpio pins are each configured using a gpxx_sel field in registers gpiocr1 or gpiocr2 with values as indicated in the tables below. when a gpio pin is configured as high impedance it can be used as an inp ut. the real - time state of gpio x can be read from gpiosr .gpiox. in addition, a latched status bit gpiosr .gpioxl is available for each gpio pin. this latched status bit is set when the transition specified by gpiocr2 .gpio13 _lsc (for gpio1 through gpio3) or by gpiocr2 .gpio47_lsc (for gpio4 through gpio7) occurs on the pin. note that gpio4 through gpio7 are alternate pin functions to tx d[7:4] and therefore are only available when the par all el mii is configured for mii, rgmii or rtbi . table 6 - 4 . gpo1, gpio1 and gpio3 configuration options gpxx_sel description 000 high impedance, not driven, can be an used as an input 001 drive logic 0 010 drive logic 1 011 interrupt output, active low. gpo1 drives low and high, gpio1 and gpio3 are open - drain. 100 output 125mhz from the tx pll 101 output 25mhz or 125 mhz from receive clock recovery pll. n ot squelched . frequency specified by cr .rcf req. 110 output real - time link status, 0=link down, 1=link up 111 reserved value, do not use table 6 - 5 . gpo2 and gpio2 configuration options gpxx_sel description 000 high impedance, not driven, can be an used as an input 001 drive logic 0 010 drive logic 1 011 reserved value, do not use 100 output 125mhz from tx pll 101 output 25 mhz or 125 mhz from receive clock reco very pll. the frequency is specified by cr .rcf req. s ignal is automatically squelched (driven low) when cr . rcsql=1 and any of several conditions occur. see section 6.2.1 . 110 output crs (carrier sense) status 111 reserved value, do not use
_________________________________________________________________________________________________ MAX24287 18 table 6 - 6 . gpio4, gpio5, gpio6 and gpio7 configuration options gpxx_sel description 000 high impedance, not driven, can be an used as an input 001 drive logic 0 010 drive logic 1 011 reserved value, do not use 100 output 125mhz from tx pll 101 output 25 mhz or 125 mhz from receive clock recovery pll. the frequency is specified by cr .rcf req. s ignal is automatically squelched (driven low) when cr . rcsql=1 and any of several conditions occur. see section 6.2.1 . 110 reserved value, do not use 111 reserved value, do not use 6.2.1 receive recovered clock squelch criteria a 25mhz or 125mhz clock from the receive clock recovery pll can be output on any of gpo2, gpio2 and gpio4 - 7. when cr . rcsql=1, this clock is squelched (driven low) when any of the following conditions occur: ? ir .alos=1 (analog loss - of - signal occurred) ? ir .rlos=1 (cdr loss - of - signal occurred)) ? ir .rlol=1 (cdr pll loss - of - lock occurred) ? ir .link_st=0 ( auto - negotiation link down occurred, latched low) since each of these criteria is a latched s tatus bit, the output clock signal remains squelched until all of these latched status bits go inactive (as described in section 7.2 ). 6.3 reset and processor interrupt 6.3.1 reset the following reset functions are availa ble in the device : 1. hardware reset pin ( rst_n ): this pin asynchronously resets all logic, state machines and registers in the device except the jtag logic . when the rst_n pin is low, all internal registers ar e reset to their default values . pin states are sampled and used to set the default values of several register fields as described in section 6.1 . rst_n should be asserted for at least 1 0 0 s. 2. global reset bit, gpiocr1 .rst: sett ing this bit is equivalent to as serting the rst_n pin. this bit is self - clearing. 3. datapath reset bit, bmcr .dp_rst. this bit resets the entire datapath from parallel mii interface through pcs encoder and decoder. it also resets the deserializer. it does not reset any registers, gpio logic, or the tx pll. the dp_rst bit is self - clearing. 4. jtag reset pin jt rst_n . this pin resets the jtag logic. see section 8 for details about jtag operation. 6.3.2 processor interrupt s any of pins gpo1, gpio1 and gpio3 can be configured as an active low interrupt output by setting the appropriate field in gpiocr1 to 011. gpo1 d rives high and low while gpio1 and gpio3 are open - drain and require pullup resistors. status bits than can cause an interrupt are located in the ir register . the corresponding interrupt enable bits are also locat ed in the ir register . the pagesel register has a top - level ir status bit to indicate the presence of
_________________________________________________________________________________________________ MAX24287 19 active interrupt sources. the pagesel register is available on all pages through the mdio interface, allowing the interrupt routine to read the register without changing the mdio page. 6.4 mdio interface 6.4.1 mdio overview the max 24287 's mdio interface is compliant to ieee 802 .3 clause 22 . max 24287 always behaves as a phy on the mdio bus. because max 24287 is not a complete phy b ut rather a device that sits between a mac and a phy, it implements only a subset of the registers and register fields specified in 802.3 claus e 22 as s hown in the table below. mdio address 802.3 name max 24287 name 0 control bmcr 1 status bmsr 2, 3 phy identifier id1 , id2 4 auto - negotiation advertisement an_adv 5 auto - negotiation link partner base page ability an_rx 6 auto - negotiation expansion an_exp 15 extended status ext_stat the m dio consists of a bidirectional, half - duplex serial data signal (mdio) and a 12.5mhz clock signal (mdc) driven by a bus master, usually a mac . the format of management frames transmitted over the mdio interface is shown below (see ieee 802.3 clause 22.2.4.5 for more information). mdio dc electrical characteristics are listed in se ction 9.2.1 . ac electrical characteristics are listed in section 9.3.6 . the max 24287 's mdio slave state machine is shown in f igure 6 - 1 . management frame fields pre st op phyad regad ta data idle read command 32 ?1?s 01 10 aaaaa rrrrr z0 16 - bit z write command 32 ?1?s 01 01 aaaaa rrrrr 10 16 - bit z the transmission and reception bit order is msb first for the phy ad, regad and data fields max 24287 supports preamble suppression. this allows quicker bursts of read and write transfers to occur by shortening the minimum transfer cycle time from 65 clock periods to 33 clock periods. there must be at least a 32- bit prea mble on the first transfer after reset, but on subsequent transfers the preamble can be suppressed or shortened. when the preamble is completely suppressed the 0 in the st symbol follows the single idle z, which is one clock period duration. like any mdio slave, max 24287 only performs the read or write operation specified if the phyad bits of the mdio command match the device phy address. the device phy address is latched during device reset from the rxd[7:4] and rx_er pins. see section 6.1 . the max 24287 does not support the 802.3 clause 45 mdio extensions. management frames with st bits other than 01 or op bits other than 01 or 10 are ignored and put the device in a state where it ignores the mdio traffic until i t sees a full preamble (32 ones). if clause 45 ics and the max 24287 are connected to the same mdio management interface, the station management entity must put a full preamble on the bus after communicating with clause 45 ics before communicating with the max 24287.
_________________________________________________________________________________________________ MAX24287 20 figure 6 - 1 . mdio slave state machine preamble init mdio=z hw reset preamble / idle mdio=z 1 32 consecutive 1s st 2 nd bit mdio=z 0 0 op 2 bits mdio=z 1 00 or 11 ta 2 bits mdio=z op=01 (write) data 16 bits mdio=z 16 clocks ta-z mdio=z ta-0 mdio=0 data 16 bits mdio=d[15:0] op=10 (read) idle mdio=z phyad 5 bits mdio=z 01 or 10 not phy mdio=z no match 24 clocks regad 5 bits mdio=z match not reg mdio=z no match 19 clocks 16 clocks
_________________________________________________________________________________________________ MAX24287 21 6.4.2 examples of max 24287 and phy management using mdio the mdio interface is typically provided by the mac function within a neighboring processor , asic or fpga c omponent. it can be used to configure the registers in the max 24287 and/or the register s in a phy or switch chip connected to the max 24287 via the sgmii interface. case 1 in figure 6 - 2 shows a typical ap plication w h ere t he max 24287 connects a mac with a 3 - speed rgmii interface to a 3 - speed phy with an sgmii interface. t hrough t he mdio interface , system software configures the max 24287 and optionally the phy. (the phy may not need to be configured if it is operat ing in a hardware - only auto - nego tiation 1000base - t mode ) . after in i tial configuration and after the phy auto - n egotiates link details with its 1000base - t link partner , the speed and mode are transferred to the max 24287 over the sgmii interface as spe cified in the sgmii specification and are available in the max 24287 an_rx register. the processor reads this information and configure s the mac and the max 24287 to match the mode the phy is in. figure 6 - 2 . management information flow options , case 1, tri - mode phy 10base-t 100base-t 1000base-t phy mac rd rxd[3:0] txd[3:0] td tclk 625 mhz rx_clk 2.5/25/125mhz (rgmii) cdr acknowledge speed contol rgmii sgmii transfer speed control gtx_clk 2.5/25/125mhz mdio case 2 in figure 6 - 3 shows a typical application w h ere the max 24287 connects a mac wit h a gmii interface to a n sgmii switch chip. through the mdio interface, system software configures the max 24287 to match the mac mode and writes the max 24287 's an_adv register to also match the mac mode . the max 24287 then transfers the speed and mode over the sgmii interface as specified in the sgmii specification. the switch chip receives this information and configures its port to match. figure 6 - 3 . management information flow options, case 2, sgmii switch chip switch chip mac rd rxd[7:0] txd[7:0] td rx_clk 125mhz gtx_clk 125mhz (gmii) cdr gmii sgmii mdio transfer speed control acknowledge speed contol case 3 in figure 6 - 4 shows a typical application w h ere the max 24287 connects a mac with a gmii in terface to an optical interface. in this case the ma x 24287 provides the 1000base - x pcs and pma functions for the optical interface. through the mdio interface, system software configures the max 24287 to match the mac mode , both of which need to be 1000 mbps speed. the max 24287 then auto - n egotiates with its link partner. this 1000base - x auto - negotiation is primarily to establish the pause functionality of the link. the max 24287 's auto - negotiation support is described in section 6.7 . MAX24287 MAX24287
_________________________________________________________________________________________________ MAX24287 22 figure 6 - 4 . management information flow options, case 3, 1000base - x interface optical interface mac rd rxd[7:0] txd[7:0] td rx_clk 125mhz gtx_clk 125mhz cdr gmii 1000base-x (e.g. sfp module) (gmii) mdio 1000base-x auto-negotiation MAX24287
_________________________________________________________________________________________________ MAX24287 23 6.5 serial interface ? 1 000base - x or sgmii the high - speed serial interface is compatible with the specification of the 1000base - cx pmd service interface tp1 as def ined in 802.3 clause 39. it is also compatible with the specification of the sgmii interface and can connect to optical pmd modules in 1000base - sx/lx interfaces. on this interface the max 24287 transmits a 1250mbaud differential signal on the tdp/tdn output pins. ddr clocking is used, and the transmit interface outputs a 625mhz differential clock signal on the tclkp/tclkn output pins. in the receive direction the clock and data recovery (cdr) block recovers both clock and data from the incoming 1250mbaud sig nal on rdp/rdn. a separate receive clock signal is not needed. signal format , coupling, termination . the serial interface passes data at 1.25 gbaud using a cml differential output and an any - format differential input . the cml tdp/tdn outputs have internal 50 ? pull up resistors to tvdd 33 . the differential input rdp/rdn does not have internal termination , and an external 100? termination resistor between rdp and rdn is recommended . the high - speed serial interface pins are typically connected with neighboring c omponents using ac coupling as shown in figure 6 - 5 . figure 6 - 5 . recommended external components for high - speed serial interface tvdd33 50? 50? 1 00 ? 50? 50? cml driver 50? 50? 1 00 ? receiver signal source signal destination 10k 10k 40k 40k rvdd33 + - 16ma receive loss - of - signal. the device's receive r logic has an alos input pin through which analog loss - of - signal (alos) can be received from a neighboring optical transceiver module, if the high - speed serial signal is transmitted/received optically. the ir .alos bit is set when the alos pin goes high. alos can cause an interrupt if enabled by ir .alos_ie. in addition, the clock - and - data recovery block (cdr) indicates loss - of - signal when it does not detect any transitions in 24 bit times. the ir .rlos latched status bit is set when the cdr indicates loss - of - signal. rlos can cause an interrupt if enabled by ir .rlos_ ie. receive loss - of - lock. the receive clock pll in the cdr locks to the recovered clock from the rdp/rdn pins and produces several receive - side clock signals. if the receive clock pll loses lock, it sets ir .rlol, which can cause an interrupt if enabled by ir .rlol_ie. transmit clock . the tclkp/tclkn differential output can be enabled and disabled using cr . tclk_en. disabled mean s the output drivers for tclkp and tclkn are disabled (high impedance) and the internal 50 ? termination resistors pull both tclkp and tclkn up to 3.3v. dc electrical characteristics. see section 9.2.2 . ac elec trical characteristics. see section 9.3.3 . max 24287 m ax 24287
_________________________________________________________________________________________________ MAX24287 24 6.6 parallel interface ? gmii, rgmii, tbi, rtbi, mii the parallel interface can be configured as gmii, mi i or tbi com pliant to ieee 802.3 clauses 35, 22 and 36 , respective ly. it can also be configured as reduced pin coun t rgmii or rtbi compliant to the hp document rgmii version 1.3 12/10/2000 . a summary of the parallel interface modes is show in table 6 - 7 below. table 6 - 7 . parallel interface modes mode baud rate, mbps data transfer per cycle, # of wires per direction transmit clock receive clock full duplex half duplex tbi, normal 1250 10 - bit codes, 10 wires input, 125mhz ou tput, 2 62.5mhz yes no tbi, 1 rx clock 1250 10 - bit codes, 10 wires input, 125mhz output, 1 125mhz yes no rtbi 1250 10 - bit codes, 5 wires, ddr input, 125mhz output, 125mhz yes no gmii 1000 8 - bit data, 8 wires input , 125mhz output, 125mhz yes no rgmii - 10 00 1000 8 - bit data, 4 wires, ddr input , 125mhz output, 125mhz yes no rgmii - 100 100 4 - bit data, 4 wires input , 25mhz output 25mhz yes yes rgmii - 10 10 4 - bit data, 4 wires input , 2.5mhz output, 2.5mhz yes yes mii - 100 dce 100 4 - bit data, 4 wires output , 25m hz output, 25mhz yes yes mii - 10 dce 10 4 - bit data, 4 wires output , 2.5mhz output, 2.5mhz yes yes mii - 100 dte 100 4 - bit data, 4 wires input , 25mhz input, 25mhz yes yes mii - 10 dte 10 4 - bit data, 4 wires input , 2.5mhz input, 2.5mhz yes yes the parallel i nterface mode is controlled by gmiicr .spd[1:0] . tbi and mii options are specified by gmiicr .tbi_rate and gmiicr . dte_dce , respectively . 6.6.1 gmii mode the max 24287 's gmii interface is compliant to ieee 802.3 clause 35 but only operates full duplex. half d uplex operation is not supported , and t he tx_er pin is ignored. the phy therefore does not receive the following from the mac: carrier extend, carrier extend error, and transmit error propagation as described in 802.3 section 35.2.1.6, section 35.2.2.5 and table 35 - 1. these features are not needed for full duplex operation. the parallel interface can be configured for gmi i mode using software configuration or pin configuration at reset . for pin configuration (see section 6.1 ) one of the following combinations of pin states must be present during device reset: ? col=0, rxd[1:0]=10 , crs=0 ? col=1, crs=0 for software configuration, the following register fields must be set: gmiicr .spd[1:0]=10 and gmiicr .ddr=0. see ieee 802.3 clause 35 for fun ctional timing diagrams. gmii dc electrical characteristics are listed in section 9.2.1 . ac electrical characteristics are listed in section 9.3.4 and 9.3.5 . table 6 - 8 . gmii parallel bus pin naming pin name 802.3 pin name function rxclk rx_clk receive 125 mhz clock output rxd[7:0] rxd [7:0] receive data output rx_dv rx_dv recei ve data valid output rx_er rx_er receive data error output crs crs receive carrier sense col col receive collision (held low in gmii mode) txclk --- outputs 125mhz from the tx pll for mac when gmiicr .txcl k_en=1. gtxclk gtx_clk transmit 125 mhz clock input txd[7:0] txd [7:0] transmit data input tx_en tx_en transmit data enable input tx_er tx_er transmit data error input (not used - ignored )
_________________________________________________________________________________________________ MAX24287 25 6.6.2 tbi mode 6.6.2.1 configuration the tbi and rtbi interfaces are used whe n a neighboring component implements the 802.3 pcs layer and therefore transmits and receives 10 - bit 8b/10b - encoded data. the parallel interface can be configured for tbi mode using software configuration or pin configuration at reset. for pin configuratio n (see section 6.1 ) device pins must be set as follows during device reset: col=0, rxd[1:0]=11, crs=0. for software configuration, the following register fields must be set: gmiicr .spd[1:0]=11 and gmiicr .ddr=0. when the parallel interface is in tbi mode, the MAX24287 does not perform 8b/10b encoding or decoding or any auto - negotiation functions. 6.6.2.2 normal tbi with two 62 .5mhz receive clocks the normal tbi interface specified in ieee 802.3 section 36.3.3 has a 10 - bit data bus in each direction, a 125mhz transmit clock (gtxclk), two 62.5mhz receive clocks (rxclk and rxclk1) and a receive comma signal. see table 6 - 9 . in the transmit path the MAX24287 samples tx_code_group [9:0] on rising edges of gtxclk. in the receive path, rxclk and rxclk1 are 180 degrees out of phase from each other (i.e. inverted) and together provide risi ng edges every 8 ns. the MAX24287 updates the rx_code_group [9:0] and comma signals before every rxclk rising edge and every rxclk1 rising edge. the neighboring component then samples rx_code_group [9:0] and comma every rxclk rising edge and every rxclk1 ris ing edge. the normal tbi interface is selected in hardware by setting rx_dv=1 during device reset or in software by setting gmiicr :tbi_rate=1. see ieee 802.3 section 36.3.3 for functional timing diagrams. tbi dc electrical characteristics are listed in section 9.2.1 . ac electrical characteristics are listed in section 9.3.4 and 9.3.5 . table 6 - 9 . tbi parallel bus pin naming (normal mode} pin name 802.3 pin name function rxclk pma_rx_clk0 receive 62.5mhz clock output phase 0, odd numbered code - groups rxd[7:0] rx_code_group [7:0] rece ive data bits 7 to 0 output rx_dv rx_code_group [8] receive data bit 8 output rx_er rx_code_group [9] receive data bit 9 output crs com_det comma detection output col --- not used txclk/rxclk1 pma_rx_clk1 receive 62.5mhz clock output phase 1, even numbe red code - groups gtxclk pma_tx_clk transmit 125mhz clock input txd[7:0] tx_code_group [7:0] transmit data bits 7 to 0 input tx_en tx_code_group [8] transmit data bit 8 input tx_er tx_code_group [9] transmit data bit 9 input 6.6.2.3 one - clock tbi mode an alternat e tbi receive clocking scheme is also available in which the two 62.5mhz receive clocks are replaced by a single 125mhz receive clock on the rxclk pin. see table 6 - 10 . in this mode a neighboring component uses rising edges of the rxclk signal to sample rx_code_group[9:0]. the alternate tbi receive clocking scheme is selected in hardware by setting rx_dv=0 during device reset or in software by setting gmiicr :t bi_rate=0. table 6 - 10 . tbi parallel bus pin naming (one - clock mode) pin name 802.3 pin name function rxclk --- receive 125mhz clock output rxd[7:0] rx_code_group [7:0] receive data bits 7 to 0 output rx_dv r x_code_group [8] receive data bit 8 output rx_er rx_code_group [9] receive data bit 9 out put crs com_det comma detection output col --- not used txclk --- outputs 125mhz from the tx pll for use by the mac when gmi icr .txclk_en=1. gtxclk pma_tx_clk transmit 125mhz clock input
_________________________________________________________________________________________________ MAX24287 26 pin name 802.3 pin name function txd[7 :0] tx_code_group [7:0] transmit data bits 7 to 0 input tx_en tx_code_group [8] transmit data bit 8 input tx_er tx_code_group [9] transmit data bit 9 input 6.6.2.4 frequency - locked throug h clocking, no buffers the refclk signal is internally multiplied to produce the 1250mhz clock used to transmit data on the serial interface tdp/tdn pins. this 1250mhz clock is also used to create the 625mhz clock on the serial interface tclkp/tclkn pins. the refclk signal must therefore be 100ppm and low jitter (<5ps rms measured using a 12khz to 2mhz bandpass filter). the rxclk and rxclk1 signals (normal tbi mode) or only the rxclk signal (one - clock tbi mode) are divided down from the 1250mhz clock recov ered from the serial data stream on the rdp/rdn pins. for proper operation in tbi mode, the signal on the gtxclk pin must be frequency locked to the signal on the refclk pin. one easy way to achieve this is to configure the MAX24287 to output on a gpio pi n a 125mhz signal from the tx pll (which is locked to the signal on the refclk pin). see section 6.2 . this 125mhz signal is then wired to a clock input on the neighboring mac/pcs component. the neighboring compo nent then uses that signal as gtxclk. 6.6.2.5 comma detection and code - group alignment in the receive path, if pcscr .en_cdet=1 then code - group alignment is per formed based on comma detection. when a comma+ pattern (0 011111xxx) or a comma ? (1100000xxx) occurs in the serial bit stream in a k28.1 or k28.5 code - group , three things happen: (1) the code - group containing the comma is output on rx_code_group [9:0] with the alignment shown in 802.3 figure 36 - 3, (2) th e comma p in is driven high, and (3) the pma_rx clocks are stretched as needed so that both rx_code_gro up[9:0] and comma are setup to be sampled by the neighboring component on the rising edge of rxclk1 (normal tbi mode) or rxclk (one - clock tbi mode). commas in k28 .7 code - groups are ignored. when pcscr .en_cdet=0, the receive path does not perform any comma detection or code - group alignment, and the comma signal is held low. 6.6.2.6 tbi control pins the MAX24287 tbi interface d oes not have the tbi en_cdet pin mentioned in 802.3 section 36.3.3. comma detection is enabled/disabled by the pcscr .en_cdet register bit instead. the MAX24287 tbi interface does not have the ewrap pin mentio ned in 802.3 section 36.3.3. control for this loopback is handled by the pcscr .tlb register bit. see section 6.10 . the MAX24287 tbi interface also does not have the ? lck_ref pin because such a control is not needed by the receive clock and data recovery block. 6.6.3 rgmii m ode the rgmii interface has three modes of operation to support three ethernet speeds: 10, 100 and 1000mbps. this document refers to these three modes as rgmii - 1000 for 1000mbps operation, rgmii - 100 for 100mbps operation and rgmii - 10 for 10mbps operation. rgmii is specified to support speed changes among the three rates as needed. the rgmii specification document can be downloaded from http:// www.hp.com/rnd/pdfs/ rgmii v1_3.pdf or can be found by a web search for "rgmii 1.3". this document also specifies the rtbi interface discussed in section 6.6.4 . the parallel interface can be configured for rgmii modes using software configuration or pin configuration at reset. for pin configuration (see section 6.1 ) one of the following combinations of pin states must be pr esent during device reset:
_________________________________________________________________________________________________ MAX24287 27 ? col=0, rxd[1:0]=xx, crs=1 (xx=00 for rgmii - 10, xx=01 for rgmii - 100, xx=10 for rgmii - 1000) ? col =1, crs=1 (rgmii - 1000 only) for software configuration, the following register fields must be set: gmiicr .spd[1:0]=xx and gmiicr .ddr=1 (where xx values are the same as shown above for rxd[1:0]). on the receive rgmii interface the MAX24287 does not report in - band status for link state, clock spe ed and duplex during normal inter - frame. this status indication is defined as optional in the rgmii specification. table 6 - 11 . rgmii parallel bus pin naming pin name rgmii pin name function rxclk rxc receive 125 mhz clock output rxd[3:0] rd[3:0] receive data bits 3 to 0 and 7 to 4 o utput rx_dv rx_ctl receive data valid output rx_er --- not used crs --- o utputs carrier sense signal col --- o utputs collision signal txclk --- outputs 125mhz from the tx pll for use by the mac when gmiicr .txclk_en=1. gtxclk txc transmit 125 mhz clock input txd[3:0] td[3:0] transmit data bits 3 to 0 and 7 to 4 input tx_en tx_ctl transmit data enable input tx_er --- not used 6.6.3.1 r gmii - 1000 mode rgmii - 1000 is a reduced pin count alternative to the gmii interface. pin count is reduced by sampling and updating data and control signals on both clock edges. for data, o nly four data lines are used, as shown in table 6 - 11. data bits 3:0 are latched on the rising edge of the clock, and data bits 7:4 are latched on the falling edge. the transmit control signals tx_en and tx_er are multiplexed onto a single tx_ctl signal. tx_en is latched on the rising edge of the transmit clock txc while a modified tx_er signal is latched on the falling edge of txc. the receive control signals rx_dv and rx_er are multiplexed on to a single rx_ctl signal. rx_dv is latched on the rising edge of the receive cloc k rxc while a modified rx_er signal is latched on the falling edge of rxc. the modified tx_er signal = ( gmii tx_er ) xor ( gmii tx_en ). the modified rx_er signal = ( gmii_rx_er ) xor ( gmii_rx_dv ) . these modifications are done to reduce power by eliminating co ntrol signal toggling at 125mhz during normal data transmission and during idle. on the transmit side of the parallel interface the max 24287 ignores the tx_er component of the tx_ctl signal , as it does in all 1000mbps interface modes , since it only operate s full - duplex at 1000mbps . therefore the 0,1 tx_ctl encoding is i nterpret ed as 0,0 (idle, normal interframe). similarly, the 1,0 tx_ctl encoding is i nterpre ted as 1,1 (normal data transmission). see the rgmii v1.3 specification document for functional tim ing diagrams. dc electrical characteristics are listed in section 9.2.1 . ac electrical characteristics are listed in section 9.3.4 and 9.3.5 . 6.6.3.2 rgmii - 10 and rgmii - 100 modes the rgmii interface can be used to convey 10 and 100mbps ethernet data. the theory of operation at these lower speeds is similar to rgmii - 1000 mode as described above but with a 2.5mhz clock for 10mbps oper ation, a 25mhz clock for 100mbps operation, and data latched and updated only on the rising edge of the clock. the rxd[3:0] pins maintain their values during the negative edge of rxclk. the control signals are conveyed on both clock edges exactly as descri bed for rgmii - 1000. see the rgmii v1.3 specification document for functional timing diagrams. dc electrical characteristics are listed in section 9.2.1 . ac characteristics are listed in section 9.3.4 and 9.3.5 .
_________________________________________________________________________________________________ MAX24287 28 6.6.3.3 clocks the rxclk clock output is 125 mhz , 25 mhz or 2.5 mhz , depending on rgmii mode. it is derived from the recovered clock from the receive serial data. the gtxclk cl ock input must be 125 mhz , 25 mhz or 2.5 mhz 100 ppm. the gtxclk clock is not used as the source of the serial data transmit clock. 6.6.4 rtbi mode the rgmii v1.3 specification document also specifies a reduced pin - count tbi interface called rtbi. this interface b ehaves similarly to the rgmii - 1000 interface specified in section 6.6.3.1 , but conveys 10 - bit data and no control information. (tbi control signals such as ewrap and en_cdet are handled by control register setti ngs.) the tx_en (tx_ctl) and rx_dv (rx_ctl) pins behave as additional data pins in this mode, as shown in table 6 - 12 . data is sampled and updated on both clock edges as is done in rgmii - 1000 mode. on the positive clock edge rxd[3:0] = rx_code_group [3:0], rx_dv = rx_code_group [4], txd[3:0] = tx_code_group [3:0] and tx_en = tx_code_group [4]. on the negative clock edge rxd[3:0] = rx_code_group [5:8], rx_dv = rx_code_group [9], txd[3:0] = tx_code_group [5:8] and t x_en = tx_code_group [9]. unlike the normal tbi interface, which has two 62.5mhz receive clocks, rtbi has a single 125mhz clock signal in each direction. the parallel interface can be configured for rtbi mode using software configuration or pin configurati on at reset. for pin configuration (see section 6.1 ) device pins must be set as follows during device reset: col=0, rxd[1:0]=11, crs=1. for software configuration, the following register fields must be set: gmiicr .spd[1:0]=11 and gmiicr .ddr=1. when the parallel interface is in rtbi mode, the MAX24287 does not perform 8b/10b encoding or decoding or any auto - negotiation functions. for proper operation in rtbi mode, the signal on the gtxclk pin must be frequency locked to the signal on the refclk pin. one easy way to achieve this is to configure the MAX24287 to output on a gpio pin a 125mhz signal from the tx pll (which is locked to the signal on the refclk pin). see section 6.2 . this 125mhz signal is then wired to a clock input on the neighboring mac/pcs component. the neighboring component then uses that signal as gtxclk. see the rgmii v1.3 specification document for functional timing diagrams. rgmii dc electrical characteristics are listed in section 9.2.1 . ac electrical characteristics are listed in section 9.3.4 and 9.3.5 . table 6 - 12 . rtbi parallel bus pin naming pin name spec pin name function rxclk rxc receive 125mhz clock output rxd[3:0] rd[3 :0] receive data bits 3 to 0 and 8 to 5 output rx_dv rx_ctl receive data bits 4 and 9 output rx_er --- not used crs com_det comma detection output col --- not used txclk --- outputs 125mhz from the tx pll for use by the mac when gmiicr .txclk_en=1. gtxclk txc transmit 125mhz clock input txd[3:0] td[3:0] transmit data bits 3 to 0 and 8 to 5 input tx_en tx_ctl transmit data bits 4 and 9 input tx_er --- not used
_________________________________________________________________________________________________ MAX24287 29 6.6.5 mii m ode the max 24287 's mii interface is compliant to ieee 802.3 clause 22 except that tx_er is ignored (and therefore the max 24287 does n o t receive transmit error propagation from the mac) . the parallel interface can be configured for mii mode using software configuration or pin configuration at reset . for pin configuration (see section 6.1 ) device pins must be set as follows during devic e reset: col=0, rxd[1:0]=0x, crs=0 (x=0 for 10mbps, x=1 for 100mbps). for software configuration, the following re gister fields must be set: gmiicr .spd[1:0]=0x and gmiicr .dd r=0. since the max 24287 can be used in a variety of applications, it can be configured to source the txclk and rxclk as a phy normally does or to accept txclk and rxclk from a neighboring component. the former case is called dc e mode; the latter is called dte mode. dte/ dce selection is controlled by the gmiicr . dte_dce register bit. in dte mode the max 24287 is configured for operation on the mac side of the mii. b oth txclk and rxclk are inputs at 2.5 mhz (10mbps mii) or 25 mhz (100mbps mii) 100 ppm. txclk is not used as the serial data transmit clock (which is derived from the refclk input instead ) . in dce mode the max 24287 is configured for operation on the phy side of the mii. b oth txclk and rxclk are out puts at 2.5 mhz or 25 mhz . the txclk output clock is derived from the refclk input. the rxclk output clock is derived from the recovered clock from the receive serial d ata when a receive signal is present or from refclk when no receive signal is present. see 802.3 clause 22 for functional timing diagrams. mii dc electrical characteristics are listed in section 9.2.1 . ac electrical characteristics are listed in section 9.3.4 and 9.3.5 . on the transmit mii interface the max 24287 requ ires that the preamble including the sfd must be an even number of nibbles (i.e. number of nibbles divided by 2 is an integer). on the receive mii interface the max 24287 always outputs an even number of nibbles of preamble. table 6 - 13 . mii parallel bus pin naming pin name 802.3 pin name function rxclk rx_clk receive 2.5 or 25 mhz clock, can be input or output rxd[3:0] rxd [3l0] receive data nibble output rx_dv rx_dv receive data valid output rx_er rx_er recei ve data error output crs crs receive carrier sense col col receive collision txclk tx_clk transmit 2.5 or 25 mhz clock, can be input or output gtxclk --- not used txd[3:0] txd [3:0] transmit data nibble input tx_en tx_en transmit data enable input tx_ er tx_er transmit data err or input ( not used - ignored )
_________________________________________________________________________________________________ MAX24287 30 6.7 auto -n egotiation (an) in the max 24287 the auto - negotiation mechanism described in ieee 802.3 clause 37 is used for auto - negotiation between ieee 802.3 1000base - x link partners as well as the transfe r of sgmii phy status to a neighboring mac as described in the cisco serial - sgmii document eng - 46158. the 802.3 1000base - x next page functionality is not supported. the pcscr . basex register bit controls the li nk timer time - out mode of the auto - negotiation protocol. the auto - negotiation mechanism between link partners use s a special code set that passes a 16 - bit value called tx_config_reg[15:0] as defined in ieee 802.3. the auto - negotiation transfer starts when bmcr . an_start is set (self clearing) and bmcr .a n_en is set . the tx_ config_reg value is continuously sent with the ack bit (bit 14) clear and the other bits sourced from the an_adv register . when the device receives a non - zero rx_ config_reg value it sets the ack bit in the tx_config_reg, saves the rx_config_reg bits to the an_rx register , and sets the an_exp .page and ir .page bit s to tell system software that a new page has arrived . the tx_config_reg transmission stops when the link ti mer times out after 10ms in 1000base - x mode or after 1.6ms in sgmii mode. system software must complete the auto - negotiation function by processing the an_rx register and configuring the hardware appropriately . the fields of the auto - negotiation registers an_adv and an_rx have different meaning s when used in 1000base - x or sgmii mode. see section 6.7.1 for 1000base - x and section 6.7.2 . for sgmii. by default, an internal watchdog timer monitors the auto - negotiation process. if the link is not up within 5 seconds after auto - negotiati on was started, the watchdog timer restarts th e auto - negotiation. this watchdog timer can be disabled by setting pcscr .wd_dis=1. 6.7.1 1000base - x auto - negotiation in 1000base - x auto - negotiation, two link partners se nd their specific capabilities to each other . each link partner compare s the capabilities that it ad vertises in its an_adv register against its link partner's advertised abilities , which are stored in the an_rx register when received . each link partner uses the same arbitration algorithm specified in ieee 802.3 clause 37.2 to determine how it should configure its hardware, and , therefore, the two link partners' co nfigurations should match . however, i f there is no overlap of capabilities between the link partners , the rf bits (remote fault, see table 6 - 14) are set to 11, and the auto - negotiation process is started again. an external processor configures the advertised abilities, reads the link partner ? s abilities , performs the arbitration algorithm , and sets the rf bits as needed . the max 24287 an block implements the auto - negotiation state machine shown in ieee 802 .3 figure 37 - 6. it also generates an internal link - down status signal whenever the an state machine is in any state other than an_disable_link_ok or link_ok. this link - down signal is used to clear the active - low bms r .link_st bit and is used to squelch output clock signals on gpio pins when cr .rcsql=1. system software can configure the max 24287 for 1000base - x auto - negotiation by setting pcscr .basex=1 and bmcr .an_en=1. the max 24287 can also be configured for 1000base - x a uto - negotiation by pin settings at reset without software configuration . in 15 - pin configuration mode (col=0 at reset), if rxd[1:0]=10 and gpo2=1 and rx_dv=1 at reset then pcscr :basex is set to 1 to indicate 1000base - x mode and bmcr .an_en is set to 1 to enable auto - negotiat ion. in 3 - pin configuration (col=1 at reset), if gpo2=1 then pcscr :basex is set to 1 to indicate 1000base - x mode and auto - negotiation is automatically enabled. in both pin configuration modes the an_adv register's reset - default value causes device capabilities to be advertised as follows: full - duplex only, no pause support, no remote fault. see section 6.1 for details a bout pin configuration at reset.
_________________________________________________________________________________________________ MAX24287 31 figure 6 - 6 . auto - n egotiation w ith a link p artner over 1000base - x link partner optical module rd td rxd[7:0] txd[7:0] rx_clk 125 mhz tx_clk 125 mhz cdr 1000base-sx/lx optical module rd td cdr basex=1 an advertisement an acknowledgement an acknowledgement an advertisement the tx_config_reg and rx_config_reg format for 1000base - x a uto - negotiation is shown in figure 6 - 7 . all reserved bits are set to 0. the ack bit is set and detected by the pcs auto - negotiation hardware. figure 6 - 7 . 1000base - x auto - negotiation tx_config_reg and rx_ config_reg fields rsvd ps1 hd fd rsvd rsvd rsvd rsvd ps2 np ack rf2 rf1 rsvd rsvd rsvd lsb msb d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 the an_adv register is the source of tx_config_reg . the received rx_config_reg is written to the an_rx register . the auto - negotiation fields for an_adv and an_rx are described in table 6 - 14 and table 6 - 15. table 6 - 14. an_adv 1000base - x auto - n egotiation ability advertisement register (mdio 4) bit(s) name description r/w reset 15 np next page capability is not supported. this b it should always be set to 0. rw 0 14 reserved ign ore on read ro 0 13: 12 rf remote fault. u sed to indicate to the link partner that a remote fault condition has been detected: 00 = no error, l ink ok 0 1 = link f ailure 10 = off l ine 11 = auto - n egotiation e rror r w 0 0 11:9 zero 1 always write 000 rw 0 8:7 p s pause. u sed to indicate pause capabilities to the link partner. 00 = no pause 0 1 = symmetric pause 10 = asymmetric pause 11 = both symmetric and asymmetric pause rw 00 6 hd u sed to indicate ability t o support half duplex to link partner. since half duplex is not supported always write 0. r w 0 5 fd u sed to indicate ability to support full duplex to link partner . 0 = do not advertise full d uplex capability 1 = advertise full d uplex capability r w 1 max 24287
_________________________________________________________________________________________________ MAX24287 32 bit(s) name description r/w reset 4: 0 zero2 always write 00000 r w 0 0000 table 6 - 15. an_rx 1000base - x auto - negotiation ability receive register (mdio 5) bit(s) name description r/w reset 15 np next page. used by l ink partner to indicate its p cs has a next page to exchange . 0 = no next page exchange request 1 = next page exchange request ro 0 14 acknowledge i ndicates link partner successfully received the previously transmitted base page . ro 0 13: 12 rf remote fault. link partner uses this fie ld to indicate a remote fa ult condition has been detected. 00 = no error, l ink ok 0 1 = link f ailure 10 = off l ine 11 = auto - n egotiation e rror ro 0 11:9 reserved ign ore on read ro 0 8:7 p s pause. used by link partner to indicate its pause capabilities. 0 0 = no pause 0 1 = symmetric pause 10 = asymmetric pause 11 = both symmetric and asymmetric pause ro 0 6 hd used by l ink partner to indicate ability to support half d uplex. 0 = n ot able to support half d uplex 1 = able to support half d uplex ro 0 5 fd us ed by link partner to indicate ability to support full duplex. 0 = n ot able to support full d uplex 1 = able to support full d uplex ro 0 4:0 reserved ign ore on read ro 0 6.7.2 sgmii control information transfer sgmii control information transfer mode is enabl ed by setting pcscr .basex=0 . according the sgmii specification, a phy sends control information to the neighboring mac using the same facilities used for 1000base - x auto - negotiation ( an_adv , an_rx , tx_config_reg, rx_config_reg, see section 6.7.1 ). since the max 24287 sits between a phy and a mac it can behave as the transmit ter or receiver in the control information transfer process depending on how it is connected to neighboring components. when the max 24287 is connected to a 1000base - t phy, for example, the phy transfers control information to the max 24287 , which then ackn owledges the information transfer. system software then reads the control information from the max 24287 and configures the max 24287 to match the phy . this situation is shown in case (a) of figure 6 - 8 . i n other scenarios, such as when the max 24287 is connected by sgmii to a switch ic, shown in case (b) of figure 6 - 8 , the max 24287 transfers control information to the neighboring component , which then ac kn owledges the information transfer . system software then reads the control information from the neighboring component and configures th at component to match the max 24287. the max 24287 an block implements the auto - negotiation state machine shown in ieee 802 .3 figure 37 - 6. it also generates an internal link - down status signal whenever the an state machine is in any state other than an_disable_link_ok or link_ok. this link - down signal is used to clear the active - low bms r .link_st bit and is used to squelch output clock signals on gpio pins when cr .rcsql=1.
_________________________________________________________________________________________________ MAX24287 33 figure 6 - 8 . sgmii control information generation, reception and acknowl edgement cat5 media phy mac rd rxd[7:0] txd[7: 0] td tclk 625 mhz rx_clk 125 mhz tx_clk 125 mhz cdr speed control - (a) phy initiated eth peripherial mdio initiate speed control acknowledge speed contol switch mac rd rxd[3:0] txd[3:0] td tclk 625 mhz rx_clk 25 mhz tx_clk 25 mhz cdr speed control - (b) device initiated (to allow switch to connect to slower peripheral mac devices) eth peripherial sdh/pdh mapper mdio m a c initiate speed control acknowledge speed contol the control information fields carried on the sgmii are: link s tatus (up /down), link speed (1000/100/10mbps) and duplex mode (full/half). the tx_config_reg and rx_config_reg format for sgmii control information transfer is shown in figure 6 - 9 . all reserved bits are set to 0. the ack bit is set and detected by the pcs hardware. figure 6 - 9 . sgmii tx_config_reg and rx_confi g_reg fields lsb msb d0 d1 d2 d3 d4 d5 d6 d7 d8 d9 d10 d11 d12 d13 d14 d15 rsvd 1 rsvd rsvd rsvd rsvd rsvd rsvd rsvd lk ack rsvd dplx spd spd rsvd when the max 24287 is the control information receiver, its an_adv register must be set to 0x0001. the received control information is automatically stored in the an_rx register. when the max 24287 is the control information transmitter, the information is sourced from its an_adv register. the max 24287 can be configured to automatically send sgmii control information by pin settings at reset without software configuration. in 15 - pin configuration mode (col=0 at reset), if rxd[1:0]=10 and gpo2=0 and rx_dv=1 at reset then pcscr :basex is set to 0 to indic ate sgmii mode, bmcr .an_en is set to 1 to enable auto - negotiation, and the an_adv spd[1:0] bits are set by the reset values of the rxd[1:0] pins. in 3 - pin configuration (col=1 at reset), if gpo2=0 then pcscr :basex is set to 0 to indicate sgmii mode , auto - negotiation is automatically enabled , and the an_adv spd[1:0] bits are set to 10 (1000mbps) . in both pin configuration modes the an_adv register's reset - default value causes device capabilities to be advertised as follows: full - duplex only, link up . see section 6.1 for details about pin configuration at reset. the an_adv register is the source of tx_config_reg value . the received rx_config_reg value is written to the an_rx register. these meaning s are described in table 6 - 16 and table 6 - 17. MAX24287 MAX24287
_________________________________________________________________________________________________ MAX24287 34 table 6 - 16. an_adv sgmii configuration information register (mdio 4) bit(s) name description r/w reset 15 lk link status. 0 = link down 1 = link up rw note 1 14 reserved ign ore on read ro 0 13 zero1 always write 0 r w 0 12 dplx d uplex mode 0 = half d uplex 1 = full duplex r w 1 11:10 spd [1:0] link s peed 00 = 10mbps 01 = 100mbps 10 = 1000mbps 11 = reserved r w note 1 9:1 zero2 always write 000000000 rw 0 0 one always write 1 r w 1 note 1: se e the an_adv regi ster description. table 6 - 17. an_rx sgmii conf iguration information receive register (mdio 5) bit(s) name description r/w reset 15 l k link partner link status. 0 = link down 1 = link up ro 0 14: 1 3 reserved i gn ore on r ead ro 0 12 dplx link partner duplex mode 0 = half duplex 1 = full duplex ro 0 1 1:10 spd link partner link speed 00 = 10mbps 01 = 100mbps 10 = 1000mbps 11 = reserved ro 0 9:0 reserved ign ore on r ead ro 0
_________________________________________________________________________________________________ MAX24287 35 6.8 data p ath s the MAX24287 data path s perform bidirectional conversion between a parallel interface (gmii, rgmii , tbi, rtbi or mii) and a 1.25gbps serial interface (1000base - x or sgmii). in gmii, rgmii and mii modes, the data path s implement the 802.3 pcs and pma sublayers including auto - negotiation . the parallel interface data is 8 bits wide. the pcs logic performs 8b/10b encoding a nd decoding. the pma logic performs 10:1 serialization and deserialization. in tbi and rtbi modes, the MAX24287 's pcs and auto - negotiation blocks are not used, and the dat a path s implements only the pma s ublayer. the parallel interface data is 10 bits wide , and the pma logic performs 10:1 serialization and deserialization. 6.8.1 gmii, rgmii and mii serial to parallel c onversion and decoding refer to the block diagram in figure 2 - 1 . clock and data are recovered f rom the incoming 1.25gbps serial signal on rdp/rdn . the serial data is then converted to 10 - bit parallel data with 10 - bit alignment determined by detecting commas. the 10 - bit code groups are then 8b/10b decoded by the pcs decoder as specified in 802.3 clau se 36. after passing through a rate adaption buffer that accounts for phase and/or frequency differences between recovered clock and mii clock, the 8 - bit data is clocked out of the device to a neighboring mac either 4 bits or 8 bits at a time. half du plex is supported in 10 and 100mbps modes but not in 1000 mbps modes. carrier extend is not supported in 1000 mbps modes. 6.8.2 gmii, rgmii and mii parallel to s erial conversion and encoding refer to the block diagram in figure 2 - 1 . parallel data is received from the mac clocked by a 125mhz, 25mhz or 2.5mhz clock , either 4 bits or 8 bits at a time. the data then passes through a rate adaption buffer that accounts for phase and/or frequency differences between mii clock and transmit clock. the 8 - bit data is then 8b/10b encoded by the pcs encoder as specified in 802.3 clause 36. the 10 - bit code - groups are then serialized. the resulting 1.25gbps serial data is transmitted to a neighboring 1000base - x optical module or sgmii - interface copper phy. half duplex is supported in 10 and 100 mbps modes but not in 1000 mbps modes. carrier extend is not supported in 1000 mbps modes. 6.8.3 tbi, rtbi serial to parallel conversion and decoding in the block diagram in figure 2 - 1 , the pcs decoder is disabled because 8b/10b decoding is not done by the MAX24287 in these modes. clock and data are recovered from the incoming 1.25gbps serial signal. the serial data is then converted to 10 - bit paralle l data with 10 - bit alignment set by detecting commas ( pcscr .en_cdet=1) or with no 10 - bit alignment (en_cdet=0, simple 10 - bit serdes mode). data is clocked out of the device to a neighboring component either 5 bits or 10 bits at a time. 6.8.4 tbi parallel to serial conversion and encoding in the block diagram in figure 2 - 1 , the pcs encoder is disabled because 8b/10b encoding is not done by the MAX24287 in these modes . parallel data is received from the mac clocked by a 125mhz clock, either 5 bits or 10 bits at a time. the 10 - bit code - groups are then serialized. the resulting 1.25gbps serial data is transmitted to a neighboring 1000base - x optical module or sgmii - interf ace copper phy. 6.8.5 rate adaption buffers, jumbo packets and clock frequency differences the MAX24287 can handle jumbo packets up to 9001 bytes long as long as the clock frequencies of each rate adaption buffer?s write clock and the read clock are both within 100ppm of nominal.
_________________________________________________________________________________________________ MAX24287 36 for example, in gmii mode the transmit rate adaption buffer is written by gtxclk and read by a 125mhz clock frequency locked to the refclk signal. if gtxclk and refclk are both maintained within 100ppm of nominal frequency then jumbo packets up to 9001 bytes long can be accommodated by the transmit rate adaption buffer. 6.9 timing path s figure 6 - 10 . timing path d iagram rx pll (cdr) deserializer serializer rx pcs decoder rx rate adaption buffer (rx buff) dlb gtxclk txclk rxclk tclkp/n rdp/rdn 125, 62.5a, 62.5b, 25, 2.5 mhz rlb 62.5b (2 clk tbi) 125, 62.5a, 25, 2.5 mhz 125, 62.5b, 25, 2.5 mhz 125, 25, 2.5 mhz 125, 62.5a, 62.5b, 25, 2.5 mhz 625m 125, 25, 12.8, 10m 625m tx pcs encoder tx rate adaption buffer (tx buff) refclk tx pll 125, 62.5a, 62.5b, 25, 2.5 mhz numbers in the tables below are clock frequencies in mhz . table 6 - 18 . timing path muxes ? no loopback mode tx rate buffer mux txclk mux/driver rx pcs mux rx rate buffer mux rxclk driver gmii gtxclk 125 -- rx pll 62.5 rx pll 125 rx pll 125 rgmii 1000 gtxclk 125 -- rx pll 62. 5 rx pll 125 rx pll 125 rgmii 100 gtxclk 25 -- rx pll 62.5 rx pll 25 rx pll 25 rgmii 10 gtxclk 2.5 -- rx pll 62.5 rx pll 2.5 rx pll 2.5 mii 100 - dce tx pll 25 tx pll 25 rx pll 62.5 rx pll 25 rx pll 25 mii 100 - dte txclk 25 --- rx pll 62.5 rxclk 25 --- mii 10 - dce tx pll 2.5 tx pll 2.5 rx pll 62.5 rx pll 2.5 rx pll 2.5 mii 10 - dte txclk 2.5 -- rx pll 62.5 rxclk 2.5 --- tbi half rate gtxclk 125 rx pll 62.5b rx pll 62.5 rx pll 62.5a rx pll 62.5a tbi full rate gtxclk 125 -- rx pll 62.5 rx pll 125 rx pll 125 rtbi gtxclk 125 -- rx pll 62.5 rx pll 125 rx pll 125 table 6 - 19 . timing path m uxes ? dlb l oopback mode tx rate buffer mux txclk mux/driver rx pcs mux rx rate buffer mux rxclk driver gmii gtxclk 125 -- tx pll 62.5 tx pll 125 tx pll 125 rgmii 1000 gtxclk 125 -- tx pll 62.5 tx pll 125 tx pll 125 rgmii 100 gtxclk 25 -- tx pll 62.5 tx pll 25 tx pll 25 rgmii 10 gtxclk 2.5 -- tx pll 62.5 tx pll 2.5 tx pll 2.5 mii 100 - dce tx pll 25 tx pll 25 tx pll 62.5 tx pll 25 tx pll 25 mii 100 - dte txclk 25 --- tx pll 62.5 txclk 25 ---
_________________________________________________________________________________________________ MAX24287 37 mode tx rate buffer mux txclk mux/driver rx pcs mux rx rate buffer mux rxclk driver mii 10 - dce tx pll 2.5 tx pll 2.5 tx pll 62.5 tx pll 2.5 tx pll 2.5 mii 10 - dte txclk 2.5 --- tx pll 62.5 txclk 2.5 --- tbi half rate gtxclk 125 tx pll 62.5b tx pll 62.5 tx pll 62.5a tx pll 62.5a tbi full rate gtxclk 125 -- tx pll 62.5 tx pll 125 tx pll 125 rtbi gtxclk 125 -- tx pll 62.5 tx pll 125 tx pll 125 table 6 - 20 . timing path muxes ? rlb l oopback mode tx rate buffer m ux txclk mux/driver rx pcs mux rx rate buffer mux rxclk driver gmii rx pll 125 -- rx pll 62.5 rx pll 125 rx pll 125 rgmii 1000 rx pll 125 -- rx pll 62.5 rx pll 125 rx pll 125 rgmii 100 rx pll 25 -- rx pll 62.5 rx pll 25 rx pll 25 rgmii 10 rx pll 2.5 -- rx pll 62.5 rx pll 2.5 rx pll 2.5 mii 100 - dce rx pll 25 tx pll 25 rx pll 62.5 rx pll 25 rx pll 25 mii 100 - dte rxclk 25 --- rx pll 62.5 rxclk 25 --- mii 10 - dce rx pll 2.5 tx pll 2.5 rx pll 62.5 rx pll 2.5 rx pll 2.5 mii 10 - dte rxclk 2.5 -- rx pll 62.5 rxclk 2.5 -- 6.9.1 rx pll the rx pll is used to recover the clock from the rd p/rdn high - speed serial input signal . it generates 625 mhz for the de - serializer and 125 mhz , 62.5 mhz , 25 mhz and 2.5 mhz for the receive - side pcs decoder, rate adaption buffer a nd parallel port logic . it also generates a loss of lock (rlol) signal for the ir .rlol latched status bit. 6.9.2 tx pll the tx pll generates a low - jitter 625mhz clock signal for the serializer and the tclkp/tclkn diff erential output . this clock signal meets the jitter requirements of ieee802.3. it also generates 125 mhz , 62.5 mhz , 25 mhz and 2.5 mhz for the transmit - side pcs decoder, rate adaption buffer and parallel port logic. the tx pll locks to the refclk signal , whic h can be 125 mhz , 25 mhz , 12.8 mhz or 10 mhz as specified by the rxd[3:2] pins during device reset . the 12.8 mhz and 10 mhz frequencies enable the device to share an oscillator with any clock synchronization ics that may be on the same board. 6.9.3 input jitter tole rance the input j itt er tolerance is specified at the r eceive seria l input rd p/rdn . the MAX24287 cdr block accepts data with maximum to tal jitter up to 0.75 ui (or 600 ps) peak - to - peak as required by 802.3 table 38 - 10 and as shown in table 9 - 8 . total jitter is composed of both deterministic and random components. the allowed random jitter equals the allowed tot al jitter minus the actual deterministic jitter at rdp/rdn. 6.9.4 output jitter generation the o utput j itter genera tion limit is specified at the t ransmit serial output (td p/tdn ) of the serializer . according to table 38 - 10 of ieee 802.3 , the maxim total jitter generated must be less than 0.24 ui (192 ps) peak - to - peak and the deterministic jitter should be l ess than 0.10 ui (80 ps) peak - to - peak . MAX24287 typical and maximum jitter generation specifications are shown in table 9 - 10 . actual output jitter performance is a function of refclk signal jitter. contac t the factory for a tool to calculate output jitter from refclk phase noise. 6.9.5 tx pll jitter transfer the tx pll has a bandwidth of approximately 200khz and jitter transfer peaking of 0.1db or less.
_________________________________________________________________________________________________ MAX24287 38 6.9.6 gpio pins as clock outputs reference clock. a 125mhz clock from the tx pll (locked to the refclk signal) can be output on one or more gpio pins. see section 6.2 for configuration details. one use for this 125mhz output is to provide a 125mhz transmit clock to a mac blo ck on a neighboring component. the mac then uses this signal to clock its transmit parallel mii pins . recovered clock. a 25mhz or 125mhz clock signal from the receive clock and data recovery pll can be output on one or more gpio pins. this clock signal is typically used in synchronous ethernet applications to send recovered ethernet line timing to the system's central timing function. see section 6.2 for configuration details. the se output clock signals do not gl itch during internal switching between frequencies or sources or when being squelched and un squelched. 6.10 loopback s three loopbacks are available in the max 24287 . the loopback data paths are shown in the block diagram in figure 2 - 1 . the clocking paths are shown in section 6.9 . 6.10.1 diagnostic loopback diagnostic loopback is enabled by setting bmcr .dlb=1. when the parallel interface is gmii, rgmii or mii, the pcs decoder in the receive path takes 10 - bit codes from the pcs encoder in the transmit path rather than from the deserializer. in these modes the rate adaption buffers are in the path , and therefore the receive clock can be different than the transmit clock . when the parallel interface is tbi or rtbi, 10 - bit codes from the transmit side of the parallel interface are looped back to the receive side of the parallel interface. i n these modes the pcs encoder and decoder blocks perform a simple pass - through function of 10 - bit codes. the single 125mhz receive clock or dual 62.5mhz receive clocks are derived from the signal on the gtxclk pin. during diagnostic loopback, if cr . dlbdo=0 the tdp/tdn output driver is placed in a high - impedance state and the tdp/tdn pins are both pulled up to 3.3v by their internal 50? termination resistors. the tclkp/tclkn output continues to toggle if enabled . if cr . dlbdo = 1 then data is transmitted on tdp /tdn during diagnostic loopback while also being looped back to the receiver . during diagnostic loopback , the col signal remain s deasserted at all times, unless bmcr .col_test is set, in which case the col signal behave s as described in 802.3 section 22.2.4.1.9. 6.10.2 terminal loopback terminal loopback is enabled by setting pcscr .tl b=1. when this loopback is enabled, the receive cdr takes serial data from the tran s mit driver rather than from the rdp/rdn pins . this loopback implements the ewrap function specified in 802.3 section 36.3.3 for the tbi interface. during terminal loopback , if cr . tlbdo=0 the tdp/tdn output driver is placed in a high - impedance state , and the tdp/tdn pins are both pulled up to 3.3v by their internal 50? termination resistors. the tclkp/tclkn output continues to togg le if enabled . if cr . tlbdo=1 then data is transmitted on t dp/tdn during terminal loopback while also being looped back to the receiver. 6.10.3 remote loopback remote loopback is enable by setting gmiicr .rlb=1. when this loopback is enabled, the transmit parallel interface logic takes data from the receive parallel interface logic rather than from the transmit parallel interface
_________________________________________________________________________________________________ MAX24287 39 pins. during remote loopback the rate adaptio n buffers, pcs encoder and decoder, and pcs auto - negotiation function all operate normally. loopback control bits bmcr .dlb and pcscr .tlb must be set to zero for c orrect remote loopback operation. rlb cannot be used in tbi or rtbi mode unless the receive signal on rdp/rdn is frequency locked to the refclk signal. if the two signals are not frequency locked the rate adaption buffers will repeated ly overflow and reset causing data errors. during remote loopback, if cr . rlbdo=0 the receive parallel interface pins rxd, rx_dv, rx_er, crs and col are all driven low. if cr . rlbdo=1 then re ceive data and control information are output on th ese pins while also being looped back to the transmitter . 6.11 diagnostic and test functions transmit pcs pattern generator. the pcs encoder has a built - in pattern generator block. these patterns provide differ ent types of jitter in order to test the performance of a downstream phy receive r . when jit_diag .jit_en=1, the pcs encoder outputs 10 - bit codes from the jitter pattern generator rather than from the 8b/10b encoding logic. the pattern to be generated is specified by jit_diag .jit_pat. patterns include low - , mixed - and high - frequency test patterns from 802.3 annex 36a as well as a custom 10 - bit pattern from the jit_diag .cust_pat register field. when jit_en is set to 1, pattern generation starts and packet transmission stops immediately. this can cut off the tail end of the packet currently being transmitted and ca n also cause a running disparity error . when jit_en is set to 0, pattern generation stops and packet transmission starts immediately. this can result in the transmission of only the tail end of a packet and can also cause a running disparity error. 6.12 data pa th latencies the max 24287 data path latencies are shown in table 6 - 21 below. these latencies exceed the full - duplex delay constraints in 802.3 table 36 - 9b. therefore MAX24287 may not be compatible with pa use operation as specified in 802.3 clause 31. table 6 - 21 . gmii data path latencies event min, ns max, ns 802.3 max, ns (#bit times) tx_en=1 sampled to 1 st bit of /s/ on tdp/tdn 119 121 108.8 (136) 1 st bit of /t/ on rdp/rdn to rx_dv deassert 211 216 153.6 (192) 6.13 board design recommendations the receive cdr block requires a stable clock signal on the refclk pin. to prevent oscillator start - up noise affecting the cdr, maxim recommends that the refclk sign al be held low during MAX24287 reset. when the refclk signal comes from a local oscillator, the easiest way to achieve this is to wire the MAX24287 rst_n signal to the enable pin on the oscillator as shown in figure 6 - 11 below. if the oscillator does not have an enable pin, then the output of the oscillator can be anded with the rst_n signal.
_________________________________________________________________________________________________ MAX24287 40 figure 6 - 11 . recommended refclk oscillator wiring rst_n oscillator en out rst_n refclk 10k MAX24287
_________________________________________________________________________________________________ MAX24287 41 7. register de scription s the device registers can be accessed through the mdio interface , which is part of the parallel mii interface. r egisters at addresses 16 to 30 are paged using the pagesel .page register field . r egis ter addresses 0 to 15 and 31 are not paged and remain the same regardless of the value of pagesel .page . non existent registers are not writable and read back as high impedance. 7.1 register map table 7 - 1 . register map mdio register address register name r/w 0 bmcr rw 1 bmsr ro 2 id1 ro 3 id2 ro 4 an_adv rw 5 an_rx ro 6 an_exp ro 15 ext_stat ro p0.16 jit_diag rw p0.17 pcscr rw p0.18 gmiicr rw p0.19 cr rw p0.20 ir rw p1.16 id ro p1.17 gpiocr1 rw p1.18 gpiocr2 rw p1.19 gpiosr ro 31 pagesel rw 7.2 register descriptions the register operatin g type is described in the ?r/w ? column using the following codes: type description rw read - write. register field can be written and read back. ro read only . register field can only be read; writing it has no effect. write 0 for future compatibility. sc self clearing. register bit self clears to 0 aft er being written as 1 lh - e latch high ? event. bit latches high when the internal event occurs and returns low when it is read. ll - e latch low ? event. bit latches low when the internal event occurs and returns high when it is read. lh - c latch high ? conditi on. bit latches high when the internal condition is present. if the condition is still present when the bit is read then the bit stays high. if the condition is not present when the bit is read then the bit returns low. ll - c latch low ? condition. bit latch es low when the internal condition is present. if the condition is still present when the bit is read then the bit stays low. if the condition is not present when the bit is read then the bit returns high. in the register definitions below, t he register address es are provided at the end of the table title , e.g. "(mdio 0)" for the bmcr register . addresses 16 to 30 are bank - switched by the pagesel .page field as sh own in table 7 - 1 . addresses 0 to 15 and 31 are not bank - switched.
_________________________________________________________________________________________________ MAX24287 42 7.2.1 bmcr basic mode cont rol register (mdio 0 ) bit(s) name description r/w reset 15 dp_rst datapath reset. this bit resets the entire datapath from parallel mii through pcs. self - clearing. see section 6.3.1 . 0 = normal operation 1 = reset r w , sc 0 14 dlb diagnostic loopback. transmit data is looped back to the receive path. see block diagram in figure 2 - 1 for the location of this loopback and see section 6.10 for additional details. 0 = disable diagnostic loopback (normal operation) 1 = enable diagnostic l oopback rw 0 13 reserved ignore on read ro 0 12 an_en auto - negotiation enable. see section 6.7 . 0 = disable 1 = enable rw note 1 11 :10 reserved ignore on read r o 0 9 an_start setting this bit causes a rest art of the auto - negotiation process. self clears. see section 6.7 . rw , sc 0 8 reserved ignore on read ro 0 7 col_test collision test. when this bit is set, max 24287 asserts the col signal within 64 parallel in terface transmit clock cycles after tx_en is asserted and deasserts the col signal within one parallel interface transmit clock cycle after tx_en is deasserted. see 802.3 section 22.2.4.1.9. see section 6.10.1 . rw 0 6: 0 reserved ignore on read ro 0 note 1: at reset when col=1 or ( rxd[1:0]!=11 and rx_dv=1) an_en is set to 1 else it is set to 0.
_________________________________________________________________________________________________ MAX24287 43 7.2.2 bmsr basic mode status register (mdio 1) bit(s) name description r/w reset 15 reserved ignore on r ead ro 0 14 spd1 00fd 100base - x full duplex capability . always indicates 1 = able to do 100base - x full duplex ro 1 13 spd100hd 100base - x half duplex capability always indicates 1 = able to do 100base - x half duplex ro 1 12 spd10fd 10mb/s full duplex capability always ind icates 1 = able to do 10mb/s full duplex ro 1 11 spd10hd 10mb/s half duplex capability always indicates 1 = able to do 10mb/s half duplex ro 1 10:9 reserved ignore on r ead ro 0 8 ext_stat extended status information available always indicates 1 = e xtend ed status information in ext_stat register ro 1 7 reserved ignore on read ro 0 6 mf_pre management preamble suppression supported always indicates 1 = mdio preamble suppression is supported. ro 1 5 an _c omp auto - negotiation complete 0 = auto - negotiation not completed or not in progress 1 = auto - negotiation h as completed ro 0 4 rfault remote fault ? indicates presence of remote fault on link partner . for sgmii, remote fault is latched high when the alos input pin goes high or wh en the cdr indicates receive loss - of - lock . for 1000base - x , remote fault is rf 00 in an_rx . rfault is latched high when a remote fault is detected. if no remote fault is detected when rfault is read then rfault goes low. otherwise rfault remains unchanged. ir . rfault is a read - only copy of this bit that can cause an interrupt when enabled. 0 = n o remote fault has been detected since this bit wa s last read 1 = remote fault has occurred since this bit was last read ro , lh - c 0 3 an_abil auto - negotiation ability always indicates 1 = able to perform auto - negotiation ro 1 2 link_st link status ? indicates the status of the physical connection to t he link partner . link_st is latched low when the link goes down. if the pcs state machine is in the link - up state when link_st is read then link_st goes high . otherwise link_st remains unchanged. ir . link_st is a read - only copy of this bit that can cause an interrupt when enabled. 0 = link down has occurred since this bit was last read 1 = link has been up continuously since this bit was last read ro , ll- c 0 1 reserved ignore on read ro 0 0 ext_cap extended reg ister capability always indicates 1 = the extended registers exist ro 1
_________________________________________________________________________________________________ MAX24287 44 7.2.3 id1 and id2 registers id1 and id2 are set to all zeroes as allowed by clause 22.2.4.3.1 of ieee 80 2.3. the actual de vice id can be read from the id register. device id 1 register (mdio 2) bit(s) name description r/w reset 15 :0 oui_hi oui[3:18] r o 0 device id 2 register (mdio 3) bit(s) name description r/w reset 15 :10 oui_li oui[19:24] r o 0 9:4 model model[5:0] model number r o 0 3:0 rev rev[3:0] revision number r o 0
_________________________________________________________________________________________________ MAX24287 45 7.2.4 an _ adv the register contents are transmitted to the link partner ?s an_rx register. the fields of this register have diff erent functions depending on whether the device i s in 1000base - x a uto - negotiation mode or in sgmii control i nformation transfer mode. see section 6.7 for details. auto - n egotiation advertisement register (mdio 4) bit(s) name description r/w reset 15 an_ adv[ 15] ( np _lk ) see section 6.7 for details. rw note 1 14 an_ adv[14] ign ore on r ead ro 0 13: 0 an_ adv [13:0] see section 6.7 for details . r w note 1 note 1: the reset v alue of the bits of this register depend on the values of configuration pins at reset, as shown below. see section 6.1. configuration pin settings at reset configuration description an_adv[15:0] reset value col=0, rx_dv=0 no auto - negotiation 0000 0000 0000 0000 col=0, rx_dv=1, rxd[1]=0 15 - pin config mode, sgmii 10 or 100mbps 10 01 0r00 0000 0001 (r = rxd[0] pin value) col=0, rx_dv=1, rxd[1]=1, gpo2=0 15 - pin config mode, sgmii 1000mbps 10 01 1000 0000 0001 col=0, rx_dv=1, rxd[1]=1, gpo2=1 15 - pin config mode, 1000base - x 0000 0000 0010 0000 col=1, gpo2=0 3 - pin config mode, sgmii 1000mbps 10 01 1000 0000 0001 col=1, gpo2=1 3- pin config mode, 1000base - x 0000 0000 0010 0000 7.2.5 an _ rx the rx_config_reg[15:0] value received from the link partner is stored in this register. this fields of this register have different functions depending on whether the device is in 1000base - x auto - negotiation mode or in sgmii control information transfer mode. see section 6.7 for details. auto - n egotiation link partner ability receive register (mdio 5) bit(s) name description r/w reset 15 np see section 6.7 for details ro 0 14 acknowledge 1= link partner successfully received the transmitted base page . ro 0 13: 0 ability see section 6.7 for details ro 0 7.2.6 an_ exp this register is used to indicate that a new link partner abilities page has been received. auto - negotiation extended status register (mdio 6) bit(s) name description r/w reset 15 : 3 reserved ignore on read ro 0 2 np next page capability - this device does not support next pages, it always reads as 0 . r o 0 1 page page received , cle ars when read . see section 6.7 . 0 = no n ew an_rx page from link partner 1 = new an_rx page from link partner is ready ro , lh - e 0 0 reserved ignore on read ro 0
_________________________________________________________________________________________________ MAX24287 46 7.2.7 ext_stat extended st atus register (mdio 15) bit( s) name description r/w reset 15 1000x _fdx 1000base - x full duplex capability. always indicates 1 = able to do 100base - x full duplex ro 1 14 1000x _hdx 1000base - x half duplex capability. always indicates 0 = not able to do 100base - x half duplex r o 0 13:0 reserved ignore on read ro 0 7.2.8 jit_diag jitter diagnostics register (mdio 0.16) bit(s) name description r/w reset 15 jit_en jitter pattern enable. enable s jitter pattern to be transmitted instead of normal data on tdp/tdn . 0 = transmit normal data patte rns from pcs encoder 1 = transmit jitter test pattern specified by jit_pat rw 0 14 :12 jit_pat jitter pattern. specifies the pattern to transmit . includes standard patterns specified in ieee 802.3 annex 36a. jit_pat pattern 000 custom pattern defined in cust_pat[9:0] 001 802.3 annex 36a .4 high frequency test pattern 1010101010? 010 802.3 annex 36a .3 mixed frequency test pattern 1111101011 0000010100? 011 low f requency pattern 1111100000? 100 " random " jitter p attern 0011111010 1001001100 1010011100 110 0010101? 101 802.3 annex 36a .2 low f requency test pattern 1111100000? 110 reserved 111 reserved . r w 0 11 : 1 0 reserved write as 0, i gnore on read ro 0 9 :0 cust_pat cust_pat[9:0] custom 10 - bit repeating pattern used when jit_pat=000 . the transmission order is lsb(0) to msb(9 ). rw 0
_________________________________________________________________________________________________ MAX24287 47 7.2.9 pcscr pcs control regi ster (mdio 0.17) bit(s) name description r/w reset 15 reserved ignore on read ro 0 1 4 tim_shrt when pcscr.basex=1 (1000base - x mode), this bit can be used to shorten the link timer timeout from 10ms to 1.6ms. the normal 10ms setting is called for in the 802.3 standard. when basex=0 this bit is ignored. 0 = pcs link timer has normal timeout 1 = pcs link timer has 1.6ms timeout rw 0 1 3 dyrx_dis disable receive pcs running disparity. 0 = enable pcs rec eive running disparity (normal) 1 = disable pcs receive running disparity rw 0 1 2 dytx_dis disable transmit pcs running disparity. 0 = enable pcs transmit running disparity (normal) 1 = disable pcs transmit running disparity rw 0 11 :7 reserved write as 0 , i gnore on read ro 0 6 wd_dis disable auto - negotiation watchdog timer . see section 6.7 . 0 = restart auto - negotiation after 5 seconds if link not up after previous start or restart 1 = d isable auto - negotiation watchdog restart rw 0 5 reserved ignore on read ro 0 4 basex specifies 1000base - x pcs mode or sgmii pcs mode . see section 6.7 . 0 = sgmii pcs mode selected , link timer = 1.6 ms 1 = 1000base - x pcs mode selecte d , link timer = 10 ms ( or 1.6ms when pcscr .tim_shrt=1 ) rw note 1 3:2 reserved write as 0, i gnore on read ro 0 1 tlb terminal loopback. transmit data is looped back to the receive path at the high - speed ser ial interface (tdp/tdn to rdp/rdn). see block diagram in figure 2 - 1 for the location of this loopback and see section 6.10 for additional details. 0 = disable terminal loopback (normal operation) 1 = enable terminal loopback rw 0 0 en_cdet enable comma detection and code group alignment in the ingress path. see section 6.6.2.5 . 0 = disable comma alignment 1 = enable comma alignment (normal operation ) rw 1 note 1: at reset, if col=1 or rxd[1] = 1 then basex is set to the value of the gpo2 pin, else basex is set to 0 . in other words, in 3- pin configuration mode or (15 - pin configuration mode and parallel interface is set to 1000mbps) basex is set to the value of the gpo2 pin. otherwise basex is set to 0.
_________________________________________________________________________________________________ MAX24287 48 7.2.10 gmiicr gmii i nterface control register (mdio 0. 18) bit(s) name description r/w reset 15 :14 spd[1:0] selects parallel mii interface mode. see section 6.6 . spd speed bus mode ddr=0 ddr=1 00 10 mbps mii rgmii - 10 01 100 mbps mii rgmii - 100 10 1000 mbps gmii rgmii - 1000 11 1000 mbps tbi rtbi rw note 1 13 tbi_rate select tbi bus receive clock mode. used when spd[1:0]=11 ; ignored otherwise. see section 6.6.2 . 0 = tbi with one 125mhz receive clock (rxclk pin) 1 = normal tbi interface: dual 62.5mhz clocks on rxclk and txclk /rxclk1 pins, 180 degrees out of phase rw note 2 12 dte _dce dte - dce mode selection for mii bus mode. used when spd[1:0]=0x and ddr=0; ignored otherwise. see section 6.6.5 . 1 = mii - dte ( MAX24287 on mac side of mii, both r x clk and txclk are in puts ) 0 = mii - dce (max24 287 on phy side of mii, both r x clk and txclk are outputs) rw note 3 11 ddr reduced pin count (rgmii or rtbi) using double data rate, i.e. data sampling/updating on both edges of the clock. see the spd[1:0] description above and section 6.6 . 0 = mii, gmii or tbi bus mode 1 = rgmii or rtbi bus mode rw note 4 10 txclk_en in gmii, rgmii and rtbi modes and in tbi mode with one 125mhz receive clock, the txclk pin is not used for parallel interface operation. the txc lk_en bit enables txclk to output a 125mhz clock from the tx pll in those modes . txclk_en is ignored in mii mode and normal tbi mode. se e section 6.6 . 0 = txclk pin is high impedance 1 = txclk pin outputs 125mhz clock rw note 5 9: 8 r eserved write as 0, ignore on read ro 0 7 r eserved write as 1, ignore on read r w 1 6:4 r eserved write as 0, ignore on read ro 0 3 ref_inv refclk invert control. 0 = noninverted 1 = inverted rw 0 2:1 r eserved write as 0, ignore o n read ro 0 0 rlb remote loopback. receive data is looped back to the transmit path. see block diagram in figure 2 - 1 for the location of this loopback and see section 6.10 for additional details. 0 = disable remote loopback (normal operation) 1 = enable remote loopback r w 0 note 1: at reset if col=0 then spd[1:0] is set to the value on the rxd[1:0] pins, else spd[1:0] is set to 10 . in other words, in 15- pin c onfiguration mode spd[1:0] is set to the value on the rxd[1:0] pins. in 3 - pin configuration mode spd[1:0] is set to 10 (1000mbps). note 2: at reset if col=0 the tbi_rate bit is set to the value on the rx_dv pin, else tbi_rate is set to 0. in other words, in 15- pin configuration mode the tbi_rate bit is set to the value on the rx_dv pin. in 3- pin configuration mode tbi_rate is set to 0. note 3: at reset if col=0 and rxd[1] = 0 the dte_dce bit is set to the value on the gpo2 pin, else dte_dce is set to 0. i n other words, in 15- pin configuration mode when the parallel interface is configured for 10mbps or 100mbps the dte_dce bit is set to the value on the gpo2 pin. otherwise the dte_dce bit is set to 0. note 4: at reset the ddr bit is set to the value o n the crs pin.
_________________________________________________________________________________________________ MAX24287 49 note 5: at reset if col=0 the txclk_en bit is set to the value on the txclk pin, else txclk_en is set to 1. in other words, in 15- pin configuration mode the txclk_en bit is set to the value on the txclk pin. in 3- pin configuration mode txclk_en is set to 1. 7.2.11 cr control register (mdio 0. 19) bit(s) name description r/w reset 15:13 r eserved write as 0, i gnore on read ro 0 12 dlbdo diagnostic loopback data out. set this bit to enable transmit data to be output on the serial interface during dia gnostic loopback (i.e. when bmcr .dlb=1 ) . see section 6.10 . rw 0 11 rlbdo remote loopback data out. set this bit to enable receive data to be output on the parallel interface during remote loopback (i.e. when gmiicr .rlb=1 ) . see section 6.10 . rw 0 10 tlbdo terminal loopback data out. set this bit to enable transmit data (rathe r than zeros) to be output on the serial interface during terminal loopback (i.e. when pcscr .tlb=1 ) . see section 6.10 . rw 0 9 rcfreq specifies which recovered cloc k frequen cy to output on a gpio pin . see section 6.2 . 0 = 25 mhz 1 = 125 mhz rw 0 8 rcsql set this bit to squelch the recovered clock on gpo2, gpio2 and gpio4 - 7 when any of several squelch conditions occur . see s ection s 6.2.1 . 0 = recovered clock output not squelched 1 = recovered clock s quelch ed when a squelch condition occurs rw 0 7:6 r eserved write as 0, i gnore on read ro 0 5 tclk_en serial interface transmit clock output enable. see section 6.5 . 0 = disab le tclkp/tclk n 1 = enable tclk p/ tclk n rw 0 4:0 r eserved write as 0, i gnore on read ro 0
_________________________________________________________________________________________________ MAX24287 50 7.2.12 ir this register contains both latched status bits and interrupt enable bits. when the latched status bit is active and the associated interrupt enable bit is set an interrupt signal can be driven onto one of the gpio pins by configuring the gpiocr1 register. interrupt register 1 (m dio 0. 20) bit(s) name description r/w reset 15 :14 reserved write as 0, ignore on read r o 0 13 rfault_ie interrupt enable for rfault. 0 = interrupt disabled 1 = interrupt enabled r o 0 12 link_st_ie interrupt enable for link_st. 0 = interrupt disabled 1 = interrupt enabled r o 0 1 1 alos _ie interrupt enable for alos. see section 6.5 . 0 = interrupt disabled 1 = interrupt enabled rw 0 1 0 page _ie interrupt enable for page . see section 6.7 . 0 = interrupt disabled 1 = interrupt enabled rw 0 9 rlol _ie interrupt enable for rlol . see section 6.5 . 0 = interrupt disabled 1 = interrupt enabled rw 0 8 rlos_ie interrupt enable fo r rlos . see section 6.5 . 0 = interrupt disabled 1 = interrupt enabled rw 0 7: 6 reserved write as 0, i gnore on read r o 0 5 rfault remote fault. this is a read - only copy of bmsr .rfault . an interrupt is generated when rfault=1 and rfault_ie=1. r o 0 4 link_st link status. this is a read - only copy of bmsr .link_st (active low). an interrupt is generated when link_st=0 and lin k_st_ie=1. r o 0 3 alos analog loss - of - signal latched status bit. set when alos input pin goes high. an interrupt is generated when alos =1 and alos_ie=1. see section 6.5 . 0 = defect not detected since last read 1 = defect detected since last read ro , lh - c 0 2 page this is a read - only copy of an_exp .page. an interrupt is generated when page=1 and page_ie=1. see section 6.7 . 0 = defect not detected since last read 1 = defect detected since last read ro 0 1 rlol receive cdr loss - of - lock latched status bit. s et when the cdr pll loses lock . an interrupt is generated when rlol=1 and rlol_ie=1. see section 6.9.1 . 0 = defect not detected since last read 1 = defect detected since last read ro , lh - c 0 0 rlos receive cdr loss - of - signal latched status bit. set when the cdr block sees no transitions in the incoming signal for 24 consecutiv e bit times. see section 6.5 . 0 = defect not detected since last read 1 = defect detected since last read r o , lh - c 0
_________________________________________________________________________________________________ MAX24287 51 7.2.13 page sel this page select register is used to extend the mdio regist er space by mapping 1 of 2 pages of 15 registers into mdio register addresses 16 to 30 . pagesel also has a global interrupt status bit . this register is available on all pages at mdio register address 31 . p age register (mdio 31, on all pages ) bit(s) name description r/w r eset 15 test factory test. always write 0. rw 0 14 reserved ignore on read r o 0 13 ir interrupt from ir register. this bit is set if any latched status bit and its associated interrupt enable bit a re both active in th e ir register. see section 6.3.2 . 0 = interrupt source not active 1 = interrupt source is active ro 0 12 :2 reserved i gnore on read r o 0 1: 0 page [1:0] page selection for mdio register addresses 16 to 30 . see section 7 . 00 = phy extended register page 0 01 = phy extended register page 1 10 , 11 = unused values rw 00
_________________________________________________________________________________________________ MAX24287 52 7.2.14 id the id register matches the jtag device id (lower 12 b its) and revision (all 4 bits). device id register (mdio 1.16) bit(s) name description r/w reset 15:12 rev rev[3:0] device revision number . c ontact factory for value. ro note 1 11:0 device device[11:0] device id ro note 1 note 1 : see device code in table 8- 2. 7.2.15 gpiocr1 gpio control register 1 ( mdio 1.17 ) bit(s) name description r/w reset 15 rst global device reset. pin states are sampled and used to set the default values of several register fields. see section 6.3.1 . 0 = normal operation 1 = reset rw , sc 0 14:12 gpo1_sel [2:0] gpo1 output pin mode selection. see table 6 - 4 . rw note 2 11:9 gpo2_sel [2:0] gpo 2 output pin mode selection. see table 6 - 5 . rw note 2 8:6 gpio1_sel [2:0] gpio1 output pin mode selection . see table 6 - 4 . rw note 1 5:3 gpio2_sel [2:0] gp io2 output pin mode selection . see table 6 - 5 . rw 000 2:0 gpio3_sel [2:0] gpio3 output pin mode selection . see table 6 - 4 . rw 000 note 1 : at reset if col =0 and gpo1 =1 the gpio1_sel bits are set to 100 (125 mhz ) , else the bits are set to 000 (high impedance) . note 2 : a t reset if col=0 and rxd[1:0]=11 (tbi or rtbi) the bits are set to 0 00 , else the bits are set to 110. 7.2.16 gpiocr2 gpio control regist er 2 (mdio 1.1 8 ) bit(s) name description r/w reset 15 :14 reserved i gnore on read ro 0 13 gpio47_lsc gpio4 - 7 latched status c ontrol. this bit controls the behavior of latched status bits gpio4l through gpio7l in gpiosr . see section 6.2 . 0 = set latched status bit when input goes low 1 = set latched status bit when input goes high rw 0 12 gpio13_lsc gpio1 - 3 latched status c ontrol. this bit controls the behavior of latched st atus bits gpio1l through gpio3l in gpiosr . see section 6.2 . 0 = set latched status bit when input goes low 1 = set latched status bit when input goes high rw 0 11 :9 gpio7_sel [2:0] gpio7 output pin mode selection . see table 6 - 6 . rw 000 8:6 gpio6_sel [2:0] gpio6 output pin mode selection . see table 6 - 6 . rw 000 5:3 gpio5_sel [2:0] gpio5 output pin mode selection . see table 6 - 6 . rw 000 2:0 gpio4_sel [2:0] gpio4 output pin mode selection . see table 6 - 6 . rw 000
_________________________________________________________________________________________________ MAX24287 53 7.2.17 gpiosr gpio status register (mdio 1.19 ) bit(s) name description r/w reset 15 reserved ignore on read ro 0 14 gpio7l gpio7 latched status. set when the transition specified by gpiocr2 .gpio47_lsc occurs on the gp io7 pin. 0 = transition did not occur since this bit was last read 1 = transition did occur since this bit was last read ro , lh - e 0 13 gpio6l gpio6 latched status. set when the transition specified by gpiocr2 .gpio47_lsc occurs on the gpio6 pin. 0 = transition did not occur since this bit was last read 1 = transition did occur since this bit was last read ro , lh - e 0 12 gpio5l gpio5 latched status. set when the transition specified by gpiocr2 .gpio47_lsc occurs on the gpio5 pin. 0 = transition did not occur since this bit was last read 1 = transition did occur since this bit was last read ro , lh - e 0 11 gpio4l gpio4 latched status. set when the transition spec ified by gpiocr2 .gpio47_lsc occurs on the gpio4 pin. 0 = transition did not occur since this bit was last read 1 = transition did occur since this bit was last read ro , lh - e 0 10 gpio3l gpio3 latched status . set when the transition specified by gpiocr2 .gpio13_lsc occurs on the gpio3 pin. 0 = transition did not occur since this bit was last read 1 = transition did occur since this bit was last read ro , lh - e 0 9 gpio2l gpio2 latched status. set when the transition specified by gpiocr2 .gpio13_lsc occurs on the gpio2 pin. 0 = transition did not occur since this bit was last read 1 = transition did occur since this bit was last read ro , lh - e 0 8 gpio1l gpio1 latched status. set when the transition specified by gpiocr2 .gpio13_lsc occurs on the gpio1 pin. 0 = transition did not occur since this bit was last read 1 = t ransition did occur since this bit was last read ro , lh - e 0 7 reserved ignore on read ro 0 6 gpio7 gpio7 pin real time status. see section 6.2 . 0 = pin low 1 = pin h igh ro 0 5 gpio6 gpio6 pin real time status . 0 = pin low 1 = pin h igh ro 0 4 gpio5 gpio5 pin real time status. 0 = pin low 1 = pin h igh ro 0 3 gpio4 gpio4 pin real time status. 0 = pin low 1 = pin h igh ro 0 2 gpio3 gpio3 pin real time status. 0 = pin low 1 = pin h igh ro 0 1 gpio2 gpio2 pin real time status. 0 = pin low 1 = pin h igh ro 0 0 gpio1 gpio1 pin real time status. 0 = pin low 1 = pin h igh ro 0
_________________________________________________________________________________________________ MAX24287 54 8. jtag and boundary scan 8.1 jtag description the max 24287 supports the standard instruction codes sample/preload, bypass, and extest. optional publi c instructions included are highz, clamp, and idcode. figure 8 - 1 shows a block diagram. the max 24287 contains the following items, which meet the requirements set by the ieee 1149.1 standard test access po rt and boundary scan architecture: test access port (tap) bypass register tap controller boundary scan register instruction register device identification register the tap has the necessary interface pins, namely jtclk, jtrst_n, jtdi, jtdo, and jtms. de tails on these pins can be found in table 5 - 4 . details about the boundary scan architecture and the tap can be found in ieee 1149.1 - 1990, ieee 1149.1a - 1993, and ieee 1149.1b - 1994. figure 8 - 1 . jtag block diagram 8.2 jtag tap controller state machine description this section discusses the operation of the t ap controller state machine. the tap controller is a finite state machine that responds to the logic level at jtms on the rising edge of jtclk. each of the states denoted in figure 8 - 2 are described in the following paragraphs. test - logic - reset. upon device power - up, the tap controller starts in the test - logic - reset state. the instruction register contains the idcode instruction. all system logic on the device operates normally. run - test - idle. run - test - idle is used between scan operations or during specific tests. the instruction register and all test registers remain idle. boundary scan register device identification register bypass register instruction register test access port controller mux select enable jtdi 50k jtms 50k jtclk jt rst_n 50k jtdo
_________________________________________________________________________________________________ MAX24287 55 select - dr - scan. all test registers retain their previous state. with jtms low, a rising edge of jtclk moves the controller into the capt ure - dr state and initiates a scan sequence. jtms high moves the controller to the select - ir - scan state. capture - dr. data can be parallel - loaded into the test register selected by the current instruction. if the instruction does not call for a parallel load or the selected test register does not allow parallel loads, the register remains at its current value. on the rising edge of jtclk, the controller goes to the shift - dr state if jtms is low or to the exit1 - dr state if jtms is high. shift - dr. the test regi ster selected by the current instruction is connected between jtdi and jtdo and data is shifted one stage toward the serial output on each rising edge of jtclk. if a test register selected by the current instruction is not placed in the serial path, it mai ntains its previous state. exit1 - dr. while in this state, a rising edge on jtclk with jtms high puts the controller in the update - dr state, which terminates the scanning process. a rising edge on jtclk with jtms low puts the controller in the pause - dr stat e. pause - dr. shifting of the test registers is halted while in this state. all test registers selected by the current instruction retain their previous state. the controller remains in this state while jtms is low. a rising edge on jtclk with jtms high put s the controller in the exit2 - dr state. exit2 - dr. while in this state, a rising edge on jtclk with jtms high puts the controller in the update - dr state and terminates the scanning process. a rising edge on jtclk with jtms low puts the controller in the shi ft - dr state. update - dr. a falling edge on jtclk while in the update - dr state latches the data from the shift register path of the test registers into the data output latches. this prevents changes at the parallel output because of changes in the shift regi ster. a rising edge on jtclk with jtms low puts the controller in the run - test - idle state. with jtms high, the controller enters the select - dr - scan state. select - ir - scan. all test registers retain their previous state. the instruction register remains unch anged during this state. with jtms low, a rising edge on jtclk moves the controller into the capture - ir state and initiates a scan sequence for the instruction register. jtms high during a rising edge on jtclk puts the controller back into the test - logic - r eset state. capture - ir. the capture - ir state is used to load the shift register in the instruction register with a fixed value. this value is loaded on the rising edge of jtclk. if jtms is high on the rising edge of jtclk, the controller enters the exit1 - i r state. if jtms is low on the rising edge of jtclk, the controller enters the shift - ir state. shift - ir. in this state, the instruction register?s shift register is connected between jtdi and jtdo and shifts data one stage for every rising edge of jtclk to ward the serial output. the parallel register and the test registers remain at their previous states. a rising edge on jtclk with jtms high moves the controller to the exit1 - ir state. a rising edge on jtclk with jtms low keeps the controller in the shift - i r state, while moving data one stage through the instruction shift register. exit1 - ir. a rising edge on jtclk with jtms low puts the controller in the pause - ir state. if jtms is high on the rising edge of jtclk, the controller enters the update - ir state an d terminates the scanning process. pause - ir. shifting of the instruction register is halted temporarily. with jtms high, a rising edge on jtclk puts the controller in the exit2 - ir state. the controller remains in the pause - ir state if jtms is low during a rising edge on jtclk. exit2 - ir. a rising edge on jtclk with jtms high puts the controller in the update - ir state. the controller loops back to the shift - ir state if jtms is low during a rising edge of jtclk in this state. update - ir. the instruction shifted into the instruction shift register is latched into the parallel output on the falling edge of jtclk as the controller enters this state. once latched, this instruction becomes the current instruction. a
_________________________________________________________________________________________________ MAX24287 56 rising edge on jtclk with jtms low puts the control ler in the run - test - idle state. with jtms high, the controller enters the select - dr - scan state. figure 8 - 2 . jtag tap controller state machine 8.3 jtag instruction register and instructions the instruction register contains a shift register as well as a latched parallel output and is 3 bits in length. when the tap controller enters the shift - ir state, the instruction shift register is connected between jtdi and jtdo. while in the shift - ir state, a rising edge on jtclk with jtms low shifts data one stage toward the serial output at jtdo. a rising edge on jtclk in the exit1 - ir state or the exit2 - ir state with jtms high moves the controller to the update - ir state. the falling edge of that same jtclk latches the data in the instruction shift register to the instruction parallel output. table 8 - 1 shows the instructions supported by the max 24287 and their respective operational binary co des. table 8 - 1 . jtag instruction codes instructions selected register instruction codes sample/preload boundary scan 010 bypass bypass 111 extest boundary scan 000 clamp bypass 011 highz bypass 100 idcod e device identification 001 test - logic - reset run - test/idle select dr- scan 1 0 capture - dr 1 0 shift - dr 0 1 exit1 - dr 1 0 pause - dr 1 exit2 - dr 1 update- dr 0 0 1 select ir- scan 1 0 capture - ir 0 shift - ir 0 1 exit1 - ir 1 0 pause - ir 1 exit2 - ir 1 update- ir 0 0 1 0 0 1 0 1 0 1
_________________________________________________________________________________________________ MAX24287 57 sample/preload. sample/reload is a mandatory instruction for the ieee 1149.1 specification. this instruction supports two functions. first, the digital i/os of the device can be sampled at the boundary scan register, using the capture - dr state, without interfering with the device?s normal operation. second, data can be shifted into the boundary scan register through jtdi using the shift - dr state. extest. extest allows testing of the interconnections to the device. when the extes t instruction is latched in the instruction register, the following actions occur: (1) once the extest instruction is enabled through the update - ir state, the parallel outputs of the digital output pins are driven. (2) the boundary scan register is connect ed between jtdi and jtdo. (3) the capture - dr state samples all digital inputs into the boundary scan register. bypass. when the bypass instruction is latched into the parallel instruction register, jtdi is connected to jtdo through the 1 - bit bypass registe r. this allows data to pass from jtdi to jtdo without affecting the device?s normal operation. idcode. when the idcode instruction is latched into the parallel instruction register, the device identification register is selected. the device id code is load ed into the device identification register on the rising edge of jtclk, following entry into the capture - dr state. shift - dr can be used to shift the id code out serially through jtdo. during test - logic - reset, the id code is forced into the instruction regi ster?s parallel o utput. highz. all digital outputs are placed into a high - impedance state. the bypass register is connected between jtdi and jtdo. clamp. all digital output pins output data from the boundary scan parallel output while connecting the bypas s register between jtdi and jtdo. the outputs do not change during the clamp instruction. 8.4 jtag test registers ieee 1149.1 requires a minimum of two test registers ? the bypass register and the boundary scan register. an optional test register, the identific ation register, has been included in the device design. it is used with the idcode instruction and the test - logic - reset state of the tap controller. bypass register. this is a single 1 - bit shift register used with the bypass, clamp, and highz instructions to provide a short path between jtdi and jtdo. boundary scan register. this register contains a shift register path and a latched parallel output for control cells and digital i/o cells. bsdl files are available at www.maxim - ic.com/techsupport/telecom/bsdl.htm . identification register. this register contains a 32 - bit shift register and a 32 - bit latched parallel output. it is selected during the idcode instruction and when the tap controller is in the test - logic - reset state. the device identification code for the max 24287 is shown in table 8 - 2 . table 8 - 2 . jtag id code device revision device code manufacturer code required MAX24287 note 1 0101 1110 1101 1111 00010100001 1 note 1: 0000 = rev a1. 0001 = rev b1. other values: contact factory.
_________________________________________________________________________________________________ MAX24287 58 9. electrical characteristics absolute maximum ratings voltage range on any signal io lead with respect to v ss ................................ ................................ - 0.3v to +5.5 v supply voltage (vdd12 ) range with respect to v ss ................................ ................................ ........ - 0.3v to +1.32 v supply voltag e (vdd33) range with respect to vss ................................ ................................ ......... - 0.3v to +3.63 v operating temperature range : industrial ................................ ................................ ............................ - 40c to +85c storage temperature range ................................ ................................ ................................ ............... - 55c to +125c lead tem perature (soldering, 10s) ................................ ................................ ................................ .................... +300 c soldering t emperature (reflow) ................................ ................................ ................................ ......................... +260 c stresses beyond those listed under ?absolute maximum ratings? may cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to the absolute maximum rating conditions for extended periods may affect device. ambient operating temperature range when device is mounted on a four - layer jedec te st board with no airflow. note 1 : the typical values listed in the tables of section 9 are not production tested. note 2: specifications to t a = - 40 c are guaranteed by design and not production tested. 9.1 recommended operating conditions table 9 - 1 . recommended dc operating conditions parameter symbol conditions min typ max units supply voltage, nominal 1.2v vdd 12 1.14 1. 2 1.26 v supply voltage, nominal 3.3v vdd33 3.135 3.3 3.465 v ambient temperature range t a - 40 +85 c junction temperature range t j - 40 +125 c 9.2 dc electrical characteristics unless otherwise stated, all specifications in this section are valid for vdd 12 = 1.2v 5 %, vdd33 = 3.3v 5% and t a = - 40c to +85c. table 9 - 2 . dc characteristics parameter symbol conditions min typ max units supply current, vdd12 pins i dd12 10, 25 or 125mhz refclk 135 ma supply current, vdd33 pin i dd 33 10, 25 or 125mhz refclk 100 m a supply current, vdd12 pins i dd12 12.8mhz refclk (note 1) 160 205 ma supply current, vdd33 pin i dd 33 12.8mhz refclk 140 175 ma input capacitance c in 4 pf output capacitance c out 7 pf note 1: when a 12.8mhz oscillator is used the tx pll use s a two- stage process to perform the frequency conversion and therefore consumes additional power.
_________________________________________________________________________________________________ MAX24287 59 9.2.1 cmos/ttl dc characteristics table 9 - 3 . dc characteristics for parallel and mdio interfaces parameter symbol co nditions min typ max units output high voltage v oh i oh = - 1ma, v dd =3.135 v 2. 4 5.5 v output low voltage v ol i ol = 1ma, v dd =3.135 v 0 0.4 v output high voltage v oh mdc, mdio. notes 1, 3 , 4 2.4 v dd v output low voltage v ol mdc, mdio. notes 2, 3 , 4 0 0. 4 v input high voltage v ih 2.0 v dd +0.2v v input low voltage v il - 0.2 0.8 v input high current i ih v in =3.3 v 1 0 a input low current, all other input pins i il v in =0 v - 1 0 a output and i/o leakage (when high impedance) i lo - 10 +10 a note 1: i oh = - 4ma note 2: i ol =4ma note 3: mdc load: 340pf max. note 4: mdio load: 340pf max plus 2k ? 5% pulldown resistor. 9.2.2 sgmii/1000base - x dc characteristics table 9 - 4 . sgmii /1000base - x transmit dc characteristi cs parameter symbol conditions min typ max units output voltage high, tdp or tdn (single - ended) v oh,dc dc - coupled. load: 50 ? pullup resistors to tvdd33 on tdp pin and on tdn pin. (note 1) v tvdd33 v output voltage low, tdp or tdn (single - ended) v ol,dc v tvdd33 ? 0.4 v output common mode voltage v ocm,dc v tvdd33 ? 0.2 v differential output voltage |v tdp ? v tdn | v od,dc 320 400 500 mv differential output voltage |v tdp ? v tdn | peak - to - peak v od,dc,pp 640 800 1000 mv p-p output common mode voltage v ocm ,ac ac - coupled to100 ? load. see figure 6 - 5 . v tvdd33 ? 0.4 v differential output voltage, |v tdp ? v tdn | v od,ac 400 mv differential output voltage, |v tdp ? v tdn | peak - to - peak v od,ac,pp 800 mv p-p o utput impedance r out single ended, to tvdd33 35 50 65 ? mismatch in a pair ? r o ut 10 % table 9 - 5 . sgmii /1000base - x receive dc characteristics parameter symbol conditions min typ max units input voltage, r dp pin v rdp 1.4 v rvdd33 v input voltage, rdn pin v rdn 1.4 v rvdd33 v input common mode voltage v icm external components as shown in figure 6 - 5 . 2.64 v input differential voltage v id |v rdp ? v rdn | 200 1600 mv
_________________________________________________________________________________________________ MAX24287 60 9.3 ac electrical characteristics unless otherwise stated, all specifications in this section are valid for vdd 12 = 1.2v 5% , vdd33 = 3.3v 5% and t a = - 40c to +85c. 9.3.1 refclk ac characteristics table 9 - 6 . refclk ac characteristics parameter symbol conditions min typ max units frequency accuracy ? f/f - 100 +100 ppm duty cycle 48 52 % rise time (20 ? 80%) t r 1 ns fall time (20 ? 80%) t f 1 ns refclk jitter: see table 9- 10 below. 9.3.2 sgmii/1000base - x interface receive ac characteristics table 9 - 7 . 1000base - x and sgmii receive ac characteristics parameter symbol conditions min typ max units input data rate , nominal f in 1250 mbps input frequency accuracy ? f/f -100 +100 p pm skew, rdp vs. rdn |t skew | note 1 20 p s note 1: m easured at 50% of the transition table 9 - 8 . 1000base - x and sgmii receive jitt er tolerance parameter symbol conditions ui p - p ps p - p rx jitter tolerance , deterministic j itter, m ax d j rd note 1 , 2 0.46 370 rx jit ter tolerance , total jitter, max t j rd note 1 , 2 0.75 600 note 1 : jitter requirements represent high- frequency jitter (abo ve 637kh z) and do not represent low - frequency jitter or wand er. random jitter = total jitter minus deterministic jitter. note 2: the bandwidth of the cdr pll is approximately 4m hz. 9.3.3 sgmii/1000base - x interface transmit ac characteristics table 9 - 9 . sgmii and 1000base - x transmit ac characteristics parameter symbol conditions min typ max units tclkp/tclkn duty cycle at 625mhz 48 52 % rise time (20 ? 80%) t r 100 200 p s fall time (20 ? 80%) t f 100 200 p s tclk edge to td valid data t clock2q note 1 250 550 ps note 1: m easured at 0v differential . does not include effects of jitter. table 9 - 10 . 1000base - x transmit jitter characteristics parameter symbol conditions typical max ui p - p ps p - p ui p - p ps p - p tx output jitter, deterministic dj td note 1 , 2 0.025 20 0.10 80 tx output jitter , total tj td note 1 , 2 0.0875 70 0.24 192 note 1 : jitter requirements represent high- frequency jitter (above 637 kh z) and do not represent low - frequency jitter or wander . random jitter = total jitter minus deterministic jitter. note 2: typical values are room - temperature measurements with a connor - winfield mx010 crystal oscillator connected to the refclk pin. note that the bandwidt h of the tx pll is in the 300- 400khz range.
_________________________________________________________________________________________________ MAX24287 61 9.3.4 parallel interface receive ac characteristics figure 9 - 1 . mii/gmii/rgmii /tbi/rtbi receive timing waveforms rx clock 5 t period t low rxd, rx_dv, rx_er, comma 6 t delay t high table 9 - 11. gmii and tbi receive ac characteristics parameter symbol conditions min typ max units rxclk period t period gmii or tbi with one 125mhz rx clock, note 5 7.5 8 8.5 ns rxclk, rxclk1 period t period normal tbi 15 16 17 ns rx clock 5 duty cycle 40 60 % rx clock 5 rising edge to rxd, rx_dv, rx_er, comma valid t delay notes 1, 6 1 5.5 ns rxclk rise time t r gmii mode, 0.7v to 1.9 v 1 ns rxclk fall time t f gmii mode, 1.9v to 0.7 v 1 ns rx clock 5 rise time t r tbi mode, 0.8 v to 2.0v 2 ns rx clock 5 fal l time t f tbi mode, 2.0v to 0.8 v 2 ns rx clock 5 slew rate rising 0.7v to 1.9v , note 2 0.6 v/ns rx clock 5 slew rate falling 1.9v to 0.7v , note 2 0.6 v/ns rxclk vs. rxclk1 skew t rcskew normal tbi mode 7.5 8 8.5 ns rxclk, rxclk1 drift rate t drift normal tbi mode, note 3 0.2 s/mhz note 1: 802.3 specifies setup and hold times for the receiver of the signals. this output delay specification has values that ensure 802.3 setup and hold specifications are met. note 2: clock sl ew rate is the instan taneous rate of change of the clock potential with respect to time (dv/dt), not an average value over the entire rise or fall time interval. conformance with this specification guarantees that the clock signals will rise and fall monotonically through the switching region. note 3: t drift is the (minimum) time for rxclk/rxclk1 to drift from 63 .5mhz to 64.5mhz or 60mhz to 59 mhz from the rxclk lock value. it is applicable under all input signal conditions (except during the code group alignment process ), inclu ding invalid or absent input signals, provided that the receiver clock recovery unit was previously locked to refclk or to a valid input signal. note 4: all specifications in this table are guaranteed by design with output load of 5pf for gmii mode and 10p f for tbi. note 5: the term "rx clock" above stands for rxclk in gmii mode, both rxclk and rxclk1 in normal tbi mode, and rxclk for tbi with one 125mhz receive clock. note 6: comma signal only applicable in tbi and rtbi modes.
_________________________________________________________________________________________________ MAX24287 62 table 9 - 12. rgmii - 1000 and rtbi receive ac characteristics parameter symbol conditions min typ max units rxclk period t period 7.5 8 8.5 ns rxclk duty cycle t low % of t period , note 1 45 55 % rxclk to rxd, rx_ctl delay t delay notes 2, 3 - 0.2 0. 8 ns rise time, all rx signals t r 20% to 80% 0.75 ns fall time, all rx signals t f 20% to 80% 0.75 ns note 1: per the rgmii spec, d uty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's cl ock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three clock cycles of the lowest speed transitioned between. note 2 : rxclk timing is from both edges in rgmii 1000 mbps mode. note 3 : the rgmii specification requires clocks to be routed such that a trace delay is added to the rxclk signal to provide sufficient setup time for rxd and rx_ctl vs. rxclk at the receiving component. note 4 : all specifications in this table are guaranteed by design with output load of 5pf. table 9 - 13. rgmii - 10/100 receive ac characteristics parameter symbol 10 mbps 100 mbps units min typ max min typ max r x clk period t period 400 40 n s r x clk duty cycle (note 4) 45 55 45 55 % rxclk to rxd, rx_ctl delay (notes 1, 2) t delay - 0.2 0. 8 - 0.2 0. 8 n s rise time, all rx signals , 20% to 80% t r 0.75 0.75 n s fall time, all rx signals , 20% to 80% t f 0.75 0.75 n s note 1 : rx clk to rxd is timed from rising edge . note 2: rx clk to rx_ ctl is timed from both rxclk edges . note 3 : per the rgmii spec, d uty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three clock cycles of the lowest speed transitioned between. note 4 : all specifications in this table are guaranteed by design with output load of 5pf. table 9 - 14 . mii ? dce receive ac characterist ics parameter symbol 10 mbps 100 mbps units min typ max min typ max rx clk period t period 400 40 ns rx clk duty cycle 45 55 45 55 % rxclk to rxd, rx_dv , rx_er delay t delay 180 230 18 30 ns note 1: rxclk is an output in this mode. note 2: 80 2.3 specifies setup and hold times, but setup and hold specifications are typically for inputs to an ic rather than outputs. this output delay specification has values that ensure 802.3 setup and hold specifications are met. note 3: all specifications in t his table are guaranteed by design with output load of 5pf.
_________________________________________________________________________________________________ MAX24287 63 table 9 - 15 . mii ? dte receive ac characteristics parameter symbol 10 mbps 100 mbps units min typ max min typ max rx clk period t period 400 40 ns rx clk duty cycle 45 55 45 55 % rxclk to rxd, rx_dv , rx_er delay t delay 0 10 0 10 ns note 1: rxclk is an input in this mode. note 2: 802.3 specifies setup and hold times, but setup and hold specifications are typically for inputs to an ic rathe r than outputs. this output delay specification has values that ensure 802.3 setup and hold specifications are met. note 3: all specifications in this table are guaranteed by design with output load of 5pf. 9.3.5 parallel interface transmit ac characteristics figure 9 - 2 . mii/gmii/rgmii /tbi/rtbi transmit timing waveforms t setup t hold tx _ clk gtx _ clk txd [7:0] tx _ en , tx _ er t period t low t high table 9 - 16. gmii, tbi, rgmii - 1000 and rtbi transmit ac characteristi cs parameter symbol conditions min typ max units input voltage low , ac v il _ac 0.9 v input voltage high , ac v ih _ac 1.7 v gtx clk period t period 7.2 8 8.8 n s gtx clk low time t low 2.5 n s gtx clk high time t high 2.5 n s gtx clk duty cycle gmii mode or tbi mode , t low % of t period 40 60 % gtx clk duty cycle rgmii - 1000 mode, t low % of t period 4 5 55 % gtxclk , txd, tx_dv, tx_er rise time t r 30% to 70% of vdd33 , note 1 0.5 2 ns gtxclk, txd, tx_dv, tx_er fall time t f 70% to 30% of vdd33 , note 1 0.5 2 ns txd, t x_dv , tx_er to gtx clk setup time t setup note 1 1 ns gtxclk to txd, t x_dv , tx_er hold time t hold note 1 0 n s note 1 : gtxclk timing is from both edges in rgmii 1000 mbps mode. note 2: all specifications in this table are guaranteed by design.
_________________________________________________________________________________________________ MAX24287 64 table 9 - 17. rgmii - 10/100 transmit ac characteristics parameter symbol 10 mbps 100 mbps units min typ max min typ max gtx clk period t period 400 40 ns gtx clk duty cycle (note 3 ) 40 60 40 60 % txd, t x_ ctl to gtx clk setup time t setup 1 1 ns g txclk to txd, tx_ctl hold time t hold 0 0 ns rise time, all t x signals , 0.5v to 2.0v t r 0.75 0.75 ns fall time, all t x signals , 0.5v to 2.0v t f 0.75 0.75 ns note 1: txclk to txd i s timed from rising edge . note 2: t xclk to tx_ctl is timed from both txclk edges . note 3 : per the rgmii spec, d uty cycle may be stretched/shrunk during speed changes or while transitioning to a received packet's clock domain as long as minimum duty cycle is not violated and stretching occurs for no more than three clock cycles of the lowest speed transitioned between. note 4 : all specifications in this table are guaranteed by design. table 9 - 18 . mii ? dce tran smit ac characteristics parameter symbol 10 mbps 100 mbps units min typ max min typ max tx clk period t period 400 40 ns tx clk duty cycle 45 55 45 55 % txd, t x_dv , tx_er to tx clk setup time t setup 6.5 6. 5 ns txclk to txd, t x_dv , tx_er hold time t hold 0 0 ns note 1: txclk is an output in this mode. note 2: all specifications in this table are guaranteed by design. table 9 - 19 . mii ? dte transmit ac characteristics parameter symbol 10 mbps 100 mbps units min typ max min typ max tx clk period t period 400 40 ns tx clk duty cycle 40 60 40 60 % txd, t x_dv , tx_er to tx clk setup time t setup 6. 5 6. 5 ns txclk to txd, t x_dv , tx_er hold time t hold 0 0 ns note 1: txclk is an in put in this mode. note 2 : all specifications in this table are guaranteed by design.
_________________________________________________________________________________________________ MAX24287 65 9.3.6 mdio i nterface ac characteristics table 9 - 20. mdio interface ac characteristics parameter symbol conditions min typ max un its mdc input period (12.5 mhz ) t1 note 1 80 ns mdc input high t2 notes 1, 2 30 ns mdc input low t3 notes 1, 2 30 ns mdio input setup time to mdc t4 note 1 10 ns mdio input hold time from mdc t5 note 1 10 ns mdc to mdio output delay t6 note 1,3 0 4 0 ns mdc to mdio high impedance t6 note 1 ,4 0 4 0 ns note 1: the input/output timing reference level for all signals is vdd33/2. all parameters are with 340pf load on mdc and 340pf load and 2k ? pulldown on mdio. note 2: all specifications in thi s table are guaranteed by design. note 3: data is valid on mdio until min delay time. note 4: when going to high impedance, data is valid until min and signal is high impedance after max. figure 9 - 3 . mdio in terface tim ing mdc t3 t4 t1 t2 t6 mdio (output) t5 mdio (input)
_________________________________________________________________________________________________ MAX24287 66 9.3.7 jtag interface ac characteristics table 9 - 21 . jtag interface timing parameter symbol min typ max units jtclk clock period t1 1000 ns jtclk clock high/low time (note 1) t2/t3 50 500 ns jtclk to jtdi, jtms setup time t4 50 ns jtclk to jtdi, jtms hold time t5 50 ns jtclk to jtdo delay t6 2 50 ns jtclk to jtdo high - impedance delay (note 2) t7 50 ns jtrst_n width low time t8 100 ns note 1 : clock can be stopped high or low. note 2: all specifications in this table are guaranteed by design. figure 9 - 4 . jtag timing diagram t1 jtdo t4 t5 t2 t3 t7 jtdi, jtms t6 jtrst _n t8 jtclk
_________________________________________________________________________________________________ MAX24287 67 10. pin assignments gvss cvdd33 refclk rst_n gtxclk dvdd33 n.c. n.c. n.c. gpio1 gpio2 gpio3 tx_er tx_en dvdd12 txd[7]/gpio7 txd[6]/gpio6 txd[5]/gpio5 txd[4]/gpio4 cvdd12 cvss tclkn tclkp tvdd33 tdn tdp tvss tvdd12 rvdd33 rdp rdn rvss rvdd12 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 n.c. 17 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 txd[3] txd[2] txd[1] txd[0] dvss txclk/rclk1 n.c. jtdo jtrst_n mdio mdc rxclk dvdd33 rxd[0] rxd[1] rxd[2] rxd[3] 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 gvdd12 alos dvdd33 jtclk jtms jtdi gpo1 gpo2 crs/comma col rx_er rx_dv dvdd12 rxd[7] rxd[6] rxd[5] rxd[4] 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 ep MAX24287 n.c. = not connected internally.
_________________________________________________________________________________________________ MAX24287 68 11. packag e and thermal information for th e latest package outline information and land patterns (footprints) , go to www.maxim - ic .com/packages . note that a ?+?, ?#?, or ? - ? in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to the package regardless of rohs status. package type package code outline no. la nd pattern no. 68 tqfn - ep (8mm x 8 mm ) t6888+1 21- 0510 90- 0354 note: the exposed pad (ep) on the bottom of this package must be connected to the ground plane. ep also functions as a heatsink. solder to the circuit - board ground plane to achieve the thermal specifications listed below. for more information about exposed pads, consult maxim's application note 3273 . table 11 - 1 . package thermal properties, natural convection parameter conditions min typ max ambient temperature note 1 - 4 0 c +85 c junction temperature - 40 c +125 c theta - ja ( ja ) note 2 20.2 c/w note 1: the package is mounted on a four - layer jedec standard test board with no airflow and dissipating maximum power. note 2: theta - ja ( ja ) is the junction to ambient t hermal resistance, when the package is mounted on a four - layer jedec standard test board with no airflow and dissipating maximum power.
_________________________________________________________________________________________________ MAX24287 maxim cannot assume responsibility for use of any circuitry other than ci rcuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408 - 737 - 7600 69 ? 2011 maxim integrated products maxim is a registered trademark of maxim integrated products. 12. data sheet revision history revision number revision date description pages changed 0 7/11 initial release ?

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